Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.

Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region and a second region. The first region includes a memory region having at least one magnetic tunnel junction (MTJ) stack, and the second region includes a logic region. An encapsulation stack is formed in the first and second regions and over the MTJ stack(s). The encapsulation stack includes a first layer, a second layer, and a third layer. A single etch may remove at least a portion of the third layer, the second layer, and the first layer of the encapsulation stack to form a self-aligned MTJ via opening over the at least one MTJ stack to form one or more peaks from the encapsulation stack above or around the MTJ stack.

Abstract: A method and device for data shunting and related to the technical field of communications are provided. The present invention solves the problem that the requirements for the Service Quality cannot be satisfied, because the shunted data can't be transmitted in the shunting network based on appointed Service Quality; and the reliability of data transmission and the system resource utilization are decreased. The method concretely comprises the following steps: the first network device of the first network determines the second Quality of Service parameter of the second network according to the first Quality of Service parameter of data to be transmitted in the first network; the first network device transmits some or all of data to be transmitted to the second network device of the second network according to the second Quality of Service parameter. The method can be applied to data shunting.

Abstract: An electronic device may be provided with wireless communications circuitry and control circuitry. The wireless communications circuitry may include millimeter wave transceiver circuitry and a phased antenna array. The phased antenna array may transmit and receive millimeter wave signals. Beam steering circuitry may be coupled to the phased antenna array and may be adjusted to steer the millimeter wave signals in a particular direction. The control circuitry may track the location of an external device using sensor data. The control circuitry may control a mechanical positioner to mechanically adjust an orientation of the phased antenna array and/or may control the beam steering circuitry to steer the millimeter wave signals towards the location of the external device. In this way, a line of sight millimeter wave communications link may be maintained between the phased antenna array and the external device even if the external device moves over time.

Abstract: An electrochemical device is disclosed. The electrochemical device includes a first transparent conductive layer, an electrochromic layer overlying the first transparent conductive layer, a counter electrode layer overlying the electrochromic layer, a second transparent conductive layer, and a switching speed parameter of not greater than 0.68 s/mm at 23° C.

Abstract: An electronic device may be provided with wireless communications circuitry and control circuitry. The wireless communications circuitry may include centimeter and millimeter wave transceiver circuitry and a phased antenna array. A dielectric cover may be formed over the phased antenna array. The phased antenna array may transmit and receive antenna signals through the dielectric cover. The dielectric cover may have a surface that faces the phased antenna array and may have a curvature. The antenna elements of the phased antenna array may be formed on a dielectric substrate. The dielectric substrate may have one or more thinned regions between antenna elements of the phased antenna array to reduce surface wave interference between adjacent antennas. The dielectric substrate may have a smaller thickness in the thinned region than in the regions under the antenna elements. The dielectric substrate may be totally removed in the thinned region.

Abstract: A structure and a manufacturing method of a metal-oxide-semiconductor field-effect transistor with an element of IVA group ion implantation are disclosed. The element of IVA group ion implantation layer is disposed in a body and close to an interface between a gate oxide layer and the body. The element of IVA group ion implantation layer is utilized to change a property of a channel of the structure.

Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.

Abstract: A device including a capping layer over a portion of a top electrode, and method of production thereof. Embodiments include an MRAM cell in a first region and a logic area in a second region of a substrate, wherein the MRAM cell includes a MTJ pillar between a top electrode and a bottom electrode; and a capping layer over a portion of the top electrode.

Abstract: An electronic device may include a phased antenna array mounted in a conductive cavity for conveying radio-frequency signals above 10 GHz. The cavity may include sidewalls extending from a rear wall. The array may include rectangular patches each having first and second perpendicular edges. Each of the first edges in the array may be aligned with a first axis. Each of the second edges in the array may be aligned with a second axis perpendicular to the first axis. The first and second axes may be oriented at 45 degrees with respect to each of the sidewalls of the cavity. Each patch may be fed using first and second positive antenna feed terminals that cover orthogonal linear polarizations. The cavity may prevent interference while symmetrically loading the impedance of both the first and second positive antenna feed terminals in each patch.

Abstract: An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antenna structures and transceiver circuitry such as millimeter wave transceiver circuitry. Antenna structures in the wireless circuitry may include patch antennas that are organized in a phased antenna array. Each patch antenna may include an antenna resonating element and a parasitic element. The parasitic element for the patch antenna may have dielectric-filled openings formed between coplanar parasitic conductors. The parasitic conductors may include a central parasitic conductor, four rectangular parasitic conductors formed around the central parasitic conductor, and corner parasitic conductors formed at the corners of the parasitic element. The corner parasitic conductors may be non-rectangular. For example, the corner parasitic conductors may have first and second perpendicular edges and a straight or curved third edge that joins the first and second edges.

Abstract: An electronic device such as a wristwatch may be provided with wireless circuitry and a display having a display module and a cover layer. The display module may include a dielectric layer. Touch sensor electrodes may be formed from conductive traces on the dielectric layer. An antenna may be embedded within the display module. The antenna may include an antenna resonating element formed from a grid of intersecting conductive traces on the dielectric layer. The grid may have edges that define a lateral outline of the antenna resonating element. The outline may have a length that configures the antenna to radiate at a desired frequency. The antenna resonating element may be formed from indium tin oxide and may be substantially transparent.

Abstract: A mechanism for locking and unlocking a photoelectric module, comprising: a base, and a handle, a clipping cover (3), a lock latch (4) and a hood placed above the base—the base is provided with a cuboid-shaped lock latch limiting slot and two sides of the lock latch limiting slot latch turning slots (1-3); an upper end on a left side face of the base (1) is provided with a handle turning slot a left end of the lock latch is a handle fitting position (4-1), an upper bottom face of a right end of the lock latch is provided with a tab (4-3), and lock latch rotation shafts (4-2)are provided between the handle fitting position and the tab solves the problems of restricted internal room of the tube shell and complicated tube shell installation procedure.

Abstract: A computer stylus may be provided that includes an elongated body with a tip and an opposing end coupled together by a shaft that includes a metal tube. The stylus may include a substrate at the end of the elongated body and conductive traces on the substrate. The traces may form a sensor electrode for a sensor and an antenna resonating element for an antenna in the stylus. The sensor may include an electrode that gathers sensor signals. Control circuitry may wirelessly transmit the sensor signals to external equipment using the antenna. The sensor electrode may be coupled to the metal tube by a filter. The filter may form an open circuit at radio-frequencies and a short circuit at the frequency of the sensor signals. The filter may mitigate deterioration in wireless performance of the antenna associated with the presence of the sensor.

Abstract: Disclosed is a gravity-adapted optical-fiber-connector comprising a gravity-adapted block and at least one gravity connector each including a fiber-stub; tail handle; rear seat being clamped and fixed by gravity-adapted block; elastic device being sleeved on a portion of excircle surface of tail handle and limited by an end face of rear seat and that of tail handle; outer sleeve and optical cable; gravity of gravity-adapted block is applied to elastic device through the end face of rear seat, after the elastic device is compressed, a spring having identical magnitude and direction with the gravity is generated and acted on the end face of tail handle, such that a physical butt-joint-surface of fiber-stub is always applied a preload about the gravity. The gravity-adapted optical-fiber-connector has stable optical-fiber coupling efficiency and coupling performance.

Abstract: A structure of a trench metal-oxide-semiconductor field-effect transistor includes an N-current spread layer (N-CSL) disposed on the N-drift region a split gate structure formed in the gate trench and covered by the insulating layer; and a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias; wherein the gate is separated from the split gate by the insulating layer to form a predetermined gap; and a depth position of a bottom of the trench gate is deeper than an interface between the P-well and the N-current spread layer.

Abstract: Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.

Abstract: To provide a communication terminal capable of suppressing an increase in power consumption of a UE during multi-subframe scheduling, a communication terminal (10) includes a monitoring unit (11) that monitors control information containing allocation information of at least one subframe where downlink data is transmitted, and a control unit (12) that determines monitoring timing to monitor the control information in accordance with a decoding result of downlink data transmitted using the at least one subframe. The monitoring unit (11) monitors the control information at the determined monitoring timing.

Abstract: Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.

Abstract: A structure of a trench metal-oxide-semiconductor field-effect transistor includes an N-current spread layer (N-CSL) disposed on the N-drift region a split gate structure formed in the gate trench and covered by the insulating layer; and a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias; wherein the gate is separated from the split gate by the insulating layer to form a predetermined gap; and a depth position of a bottom of the trench gate is deeper than an interface between the P-well and the N-current spread layer.