Abstract: Embodiments of the present invention relate to a data shunting method, a data transmission device and a shunting node device, the data shunting method provided in the embodiments of the present invention includes: acquiring the number of to-be-transmitted shunted data packets which are cached in the shunting node device; when the number of the to-be-transmitted shunted data packets is less than a first threshold value, transmitting shunted data to the shunting node device, otherwise, not transmitting the shunted data to the shunting node device. The data shunting method provided in the embodiments of the present invention enables the data transmission device to provide the shunting node device with an appropriate shunted data rate.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.

Abstract: Embodiments of the present disclosure relate to a method, device and computer program product for software bug verification. In one embodiment, the method includes determining a test action for verification of a software bug to be verified based on an identification of the software bug. The method further includes determining similarities between the test action and a plurality of historical test actions. The method further includes in response to a similarity between the test action and at least one of the plurality of historical test actions exceeding a threshold similarity, associating the test action with a code fragment category associated with the at least one historical test action. The method further includes verifying the software bug by running one code fragment in the code fragment category.

Abstract: An electronic device may include a substrate and a conductive layer on the substrate. The conductive layer may be patterned to form a first region and a second region that surrounds and defines the shape of the first region. The first region may be formed from a continuous portion of the conductive layer. The second region may include a grid of openings that divides the conductive layer into an array of patches. The first region may form an antenna resonating element for an antenna. The second region may block antenna currents from the antenna resonating element and may be transparent to radio-frequency electromagnetic waves. The openings may have a width that is too narrow to be discerned by the human eye. This may configure the first and second regions to appear as a single continuous conductive layer despite the fact that an antenna resonating element is formed therein.

Abstract: A computer stylus may be provided that includes an elongated body with a tip and an opposing end coupled together by a shaft that includes a metal tube. The stylus may include a substrate at the end of the elongated body and conductive traces on the substrate. The conductive traces on the substrate may form an antenna ground, an antenna resonating element arm, and a return path. The antenna resonating element arm may be a helical structure that wraps around the substrate. The antenna ground formed from the conductive traces may be coupled to the metal tube using an intermediate metal layer. A cap structure formed at the opposing end and over the substrate may be interposed between the conductive traces and adhesive to protect the conductive traces from the adhesive. A metal portion of the cap structure may serve as an antenna signal reflector.

Abstract: Integrated circuits and methods for fabricating magnetic tunnel junction (MTJ) structures and integrated circuits are provided. An exemplary method for fabricating an integrated circuit including a magnetic tunnel junction (MTJ) structure includes forming magnetic tunnel junction (MTJ) layers over a substrate. Further, the method includes forming a conductive pillar over the MTJ layers, wherein the conductive pillar is formed with an uppermost surface, and wherein the uppermost surface is not planarized. Also, the method includes etching the MTJ layers to form a pillar structure from portions of the MTJ layers underlying the conductive pillar.

Abstract: An electronic device may be provided with a phased antenna array for conveying millimeter wave signals. The array may be mounted to a substrate that includes transmission line layers having a first dielectric permittivity and antenna layers having a second dielectric permittivity that is less than the first dielectric permittivity. A ground plane may be interposed between the antenna layers and the transmission line layers. The array may be mounted to the antenna layers and transceiver circuitry may be mounted to the transmission line layers. Transmission line traces may be formed on the transmission line layers. The relatively high permittivity of the first set of dielectric layers may allow the transmission line traces to be routed relatively close together with minimal electromagnetic interference. The relatively low permittivity of the second set of dielectric layers may allow the array to operate with satisfactory antenna efficiency, gain, and bandwidth.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.

Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region and a second region. The first region includes a memory region having at least one magnetic tunnel junction (MTJ) stack, and the second region includes a logic region. An encapsulation stack is formed in the first and second regions and over the MTJ stack(s). The encapsulation stack includes a first layer, a second layer, and a third layer. A single etch may remove at least a portion of the third layer, the second layer, and the first layer of the encapsulation stack to form a self-aligned MTJ via opening over the at least one MTJ stack to form one or more peaks from the encapsulation stack above or around the MTJ stack.

Abstract: A method and device for data shunting and related to the technical field of communications are provided. The present invention solves the problem that the requirements for the Service Quality cannot be satisfied, because the shunted data can't be transmitted in the shunting network based on appointed Service Quality; and the reliability of data transmission and the system resource utilization are decreased. The method concretely comprises the following steps: the first network device of the first network determines the second Quality of Service parameter of the second network according to the first Quality of Service parameter of data to be transmitted in the first network; the first network device transmits some or all of data to be transmitted to the second network device of the second network according to the second Quality of Service parameter. The method can be applied to data shunting.

Abstract: An electronic device may be provided with wireless communications circuitry and control circuitry. The wireless communications circuitry may include millimeter wave transceiver circuitry and a phased antenna array. The phased antenna array may transmit and receive millimeter wave signals. Beam steering circuitry may be coupled to the phased antenna array and may be adjusted to steer the millimeter wave signals in a particular direction. The control circuitry may track the location of an external device using sensor data. The control circuitry may control a mechanical positioner to mechanically adjust an orientation of the phased antenna array and/or may control the beam steering circuitry to steer the millimeter wave signals towards the location of the external device. In this way, a line of sight millimeter wave communications link may be maintained between the phased antenna array and the external device even if the external device moves over time.

Abstract: An electrochemical device is disclosed. The electrochemical device includes a first transparent conductive layer, an electrochromic layer overlying the first transparent conductive layer, a counter electrode layer overlying the electrochromic layer, a second transparent conductive layer, and a switching speed parameter of not greater than 0.68 s/mm at 23° C.

Abstract: An electronic device may be provided with wireless communications circuitry and control circuitry. The wireless communications circuitry may include centimeter and millimeter wave transceiver circuitry and a phased antenna array. A dielectric cover may be formed over the phased antenna array. The phased antenna array may transmit and receive antenna signals through the dielectric cover. The dielectric cover may have a surface that faces the phased antenna array and may have a curvature. The antenna elements of the phased antenna array may be formed on a dielectric substrate. The dielectric substrate may have one or more thinned regions between antenna elements of the phased antenna array to reduce surface wave interference between adjacent antennas. The dielectric substrate may have a smaller thickness in the thinned region than in the regions under the antenna elements. The dielectric substrate may be totally removed in the thinned region.

Abstract: A structure and a manufacturing method of a metal-oxide-semiconductor field-effect transistor with an element of IVA group ion implantation are disclosed. The element of IVA group ion implantation layer is disposed in a body and close to an interface between a gate oxide layer and the body. The element of IVA group ion implantation layer is utilized to change a property of a channel of the structure.

Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.

Abstract: A device including a capping layer over a portion of a top electrode, and method of production thereof. Embodiments include an MRAM cell in a first region and a logic area in a second region of a substrate, wherein the MRAM cell includes a MTJ pillar between a top electrode and a bottom electrode; and a capping layer over a portion of the top electrode.

Abstract: An electronic device may include a phased antenna array mounted in a conductive cavity for conveying radio-frequency signals above 10 GHz. The cavity may include sidewalls extending from a rear wall. The array may include rectangular patches each having first and second perpendicular edges. Each of the first edges in the array may be aligned with a first axis. Each of the second edges in the array may be aligned with a second axis perpendicular to the first axis. The first and second axes may be oriented at 45 degrees with respect to each of the sidewalls of the cavity. Each patch may be fed using first and second positive antenna feed terminals that cover orthogonal linear polarizations. The cavity may prevent interference while symmetrically loading the impedance of both the first and second positive antenna feed terminals in each patch.

Abstract: An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antenna structures and transceiver circuitry such as millimeter wave transceiver circuitry. Antenna structures in the wireless circuitry may include patch antennas that are organized in a phased antenna array. Each patch antenna may include an antenna resonating element and a parasitic element. The parasitic element for the patch antenna may have dielectric-filled openings formed between coplanar parasitic conductors. The parasitic conductors may include a central parasitic conductor, four rectangular parasitic conductors formed around the central parasitic conductor, and corner parasitic conductors formed at the corners of the parasitic element. The corner parasitic conductors may be non-rectangular. For example, the corner parasitic conductors may have first and second perpendicular edges and a straight or curved third edge that joins the first and second edges.

Abstract: An electronic device such as a wristwatch may be provided with wireless circuitry and a display having a display module and a cover layer. The display module may include a dielectric layer. Touch sensor electrodes may be formed from conductive traces on the dielectric layer. An antenna may be embedded within the display module. The antenna may include an antenna resonating element formed from a grid of intersecting conductive traces on the dielectric layer. The grid may have edges that define a lateral outline of the antenna resonating element. The outline may have a length that configures the antenna to radiate at a desired frequency. The antenna resonating element may be formed from indium tin oxide and may be substantially transparent.

Abstract: A mechanism for locking and unlocking a photoelectric module, comprising: a base, and a handle, a clipping cover (3), a lock latch (4) and a hood placed above the base—the base is provided with a cuboid-shaped lock latch limiting slot and two sides of the lock latch limiting slot latch turning slots (1-3); an upper end on a left side face of the base (1) is provided with a handle turning slot a left end of the lock latch is a handle fitting position (4-1), an upper bottom face of a right end of the lock latch is provided with a tab (4-3), and lock latch rotation shafts (4-2)are provided between the handle fitting position and the tab solves the problems of restricted internal room of the tube shell and complicated tube shell installation procedure.