Patents by Inventor Yi Jiang

Yi Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194498
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
  • Patent number: 10686252
    Abstract: An electronic device may be provided with wireless circuitry that includes a radio-frequency transceiver circuit and an antenna. The antenna may be a patch antenna formed from a patch antenna resonating element and an antenna ground. The patch antenna resonating element may be formed from a metal patch on a printed circuit board. The antenna ground may be formed from a metal housing having a planar rear wall that lies in a plane parallel to the metal patch. The radio-frequency transceiver circuit may be coupled to the metal patch through traces on the printed circuit and may be coupled to rear wall of the housing through a screw and a screw boss in the housing. Buttons and other electrical components may be mounted on the printed circuit board and may be coupled to control circuitry on the printed circuit board through the metal patch.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: June 16, 2020
    Assignee: Apple Inc.
    Inventors: Siwen Yong, Qingxiang Li, Yi Jiang, Robert W. Schlub, Umar Azad, Rodney A. Gomez Angulo, Enrique Ayala Vazquez
  • Patent number: 10684421
    Abstract: Disclosed is a gravity-adapted optical-fiber-connector comprising a gravity-adapted block and at least one gravity connector each including a fiber-stub; tail handle; rear seat being clamped and fixed by gravity-adapted block; elastic device being sleeved on a portion of excircle surface of tail handle and limited by an end face of rear seat and that of tail handle; outer sleeve and optical cable; gravity of gravity-adapted block is applied to elastic device through the end face of rear seat, after the elastic device is compressed, a spring having identical magnitude and direction with the gravity is generated and acted on the end face of tail handle, such that a physical butt-joint-surface of fiber-stub is always applied a preload about the gravity. The gravity-adapted optical-fiber-connector has stable optical-fiber coupling efficiency and coupling performance.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: June 16, 2020
    Assignee: Accelink Technologies Co., Ltd.
    Inventors: Xiaobo Zhao, Xinhai Zhu, Zhechi Lu, Wenchuang Gao, Yi Jiang, Benqing Quan, Yuxiang Yang
  • Patent number: 10680663
    Abstract: An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antennas. The antennas may include phased antenna arrays each of which includes multiple antenna elements. Phased antenna arrays may be mounted along edges of a housing for the electronic device, behind a dielectric window such as a dielectric logo window in the housing, in alignment with dielectric housing portions at corners of the housing, or elsewhere in the electronic device. A phased antenna array may include arrays of patch antenna elements on dielectric layers separated by a ground layer. A baseband processor may distribute wireless signals to the phased antenna arrays at intermediate frequencies over intermediate frequency signal paths. Transceiver circuits at the phased antenna arrays may include upconverters and downconverters coupled to the intermediate frequency signal paths.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 9, 2020
    Assignee: Apple Inc.
    Inventors: Yuehui Ouyang, Yi Jiang, Matthew A. Mow, Basim Noori, Mattia Pascolini, Ruben Caballero
  • Patent number: 10676828
    Abstract: A composite can include a substrate and a conversion coating overlying the substrate and comprising at least one of a zirconium oxide, a hafnium oxide, or a combination thereof. The conversion coating can be formed from a zirconia or hafnia-based complex obtained by reacting at least one of a zirconium ion source, a hafnium ion source, or a combination thereof, with a chelating compound in a reaction and another chelating compound in another reaction.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: June 9, 2020
    Assignee: SAINT-GOBAIN PERFORMANCE PLASTICS CORPORATION
    Inventors: Nazila Dadvand, Nafih Mekhilef, Yi Jiang, Raymond J. White
  • Publication number: 20200176485
    Abstract: The present disclosure provides an array substrate, a method for manufacturing the array substrate, and a display device. A low temperature polysilicon includes a base layer, a low temperature polysilicon layer, a gate insulating layer, gate electrodes, and an interlayer dielectric layer. The low temperature polysilicon layer is formed on the base layer. The gate insulating layer is formed on the low temperature polysilicon layer. The gate electrodes are formed on the gate insulating layer. The interlayer dielectric layer covers the gate electrodes and the gate insulating layer. In the method for manufacturing the array substrate, hydriding the low temperature polysilicon layer is arranged before coating the interlayer dielectric layer; the interlayer dielectric layer is formed with a high temperature following the hydriding process to eliminate rapid thermal annealing activation, to simplify the industry procedure, and to save the energy consumption and the cost.
    Type: Application
    Filed: January 2, 2019
    Publication date: June 4, 2020
    Inventor: Yi JIANG
  • Publication number: 20200162961
    Abstract: A method and device for data shunting and related to communications are provided. The method includes: determining, by the first network device of the first network, the second Quality of Service parameter of the second network according to the first Quality of Service parameter of data to be transmitted in the first network; transmitting, by the first network device, some or all of data to be transmitted to the second network device of the second network according to the second Quality of Service parameter. According to the application, the shunted data can be transmitted in the shunting network based on appointed Service Quality, thereby the requirements for the Service Quality can be satisfied, and the reliability of data transmission and the system resource utilization are increased.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Yi JIANG, Wei QUAN, Weiwei SONG
  • Patent number: 10651380
    Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region. A base dielectric layer is arranged over the substrate. The base dielectric layer includes an interconnect in the first region. A first electrode is arranged over the interconnect in the first region. A mask structure is arranged over the first electrode. At least one spacer stack is arranged at least partially around the mask structure and the first electrode. The spacer stack(s) includes a resistive switching element at least partially lining sidewalls of the mask structure and the first electrode, and a second electrode arranged over the resistive switching element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Patent number: 10645732
    Abstract: Embodiments of the present invention provide a method, a device, and a system for determining timing advance grouping, and relate to the field of communications, the method, device and system for determining timing advance grouping. The method includes adding, by a base station (eNodeB), a component carrier (CC) for a user equipment (UE); according to obtained timing advance (TA) group information or a preset rule, determining a TA group that the added CC belongs to, where the TA group is a set of CCs that can share a TA; and sending identification information that identifies the TA group to the UE. Embodiments of the present invention are used to determine TA grouping when the eNodeB adds the CC for the UE.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 5, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yi Jiang, Zhongbin Qin, Yinghui Yu, Junren Chang, Mingzeng Dai, Guanglin Han, Wei Quan, Jian Zhang, Qiao Zhang, Yajuan Li, Boyun Xie, Yi Guo, Pingping Xing
  • Publication number: 20200136697
    Abstract: The present invention belongs to the technical field of common signal transmission, and specifically relates to a CS-based omnidirectional beamforming design method in a uniform rectangular array. The main purpose of the present invention is to handle the beamforming design for realizing cell-level coverage in downlink transmission of common signals. For a large-size antenna base station with a uniform rectangular array, the present invention provides two omnidirectional beamforming design schemes: beamforming design based on complementary sequence sets and CCC-based beamforming design. Both schemes can obtain a completely smooth beam pattern in each direction, with low complexity and closed-form solution. Furthermore, most complementary sequence sets and code words of the complete complementary codes show a constant modulus, so that the whole beamforming scheme can be efficiently realized only by using the simulation-domain beamforming architecture. The hardware efficiency is effectively improved.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 30, 2020
    Inventors: Yi JIANG, Dongliang SU, Xin WANG
  • Publication number: 20200121240
    Abstract: The present disclosure relates to noninvasive methods for detecting liver fibrosis. Disclosed herein are noninvasive liver fibrosis detection methods that use Doppler Ultrasound devices and a physics-based machine learning method. Further disclosed herein are methods for detecting liver fibrosis in a subject by detecting and measuring the presence of a shift in the frequency of blood flow in the hepatic vein as compared to the frequency of blood flow in the portal vein.
    Type: Application
    Filed: June 29, 2018
    Publication date: April 23, 2020
    Inventors: Yi JIANG, Hao CHEN, Bin ZHANG, Sergey KLIMOV
  • Publication number: 20200127197
    Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contact formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 23, 2020
    Inventors: Curtis Chun-I HSIEH, Wei-Hui HSU, Wanbing YI, Yi JIANG, Juan Boon TAN
  • Patent number: 10627922
    Abstract: A computer stylus may be provided that includes an elongated body with a tip and an opposing end coupled together by a shaft that includes a metal tube. The stylus may include a substrate at the end of the elongated body and conductive traces on the substrate. The conductive traces on the substrate may form an antenna ground, an antenna resonating element arm, and a return path. The antenna resonating element arm may be a helical structure that wraps around the substrate. The antenna ground formed from the conductive traces may be coupled to the metal tube using an intermediate metal layer. A cap structure formed at the opposing end and over the substrate may be interposed between the conductive traces and adhesive to protect the conductive traces from the adhesive. A metal portion of the cap structure may serve as an antenna signal reflector.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 21, 2020
    Assignee: Apple Inc.
    Inventors: Lu Zhang, Yi Jiang, Mattia Pascolini
  • Patent number: 10630801
    Abstract: Embodiments of the present invention relate to a data shunting method, a data transmission device and a shunting node device, the data shunting method provided in the embodiments of the present invention includes: acquiring the number of to-be-transmitted shunted data packets which are cached in the shunting node device; when the number of the to-be-transmitted shunted data packets is less than a first threshold value, transmitting shunted data to the shunting node device, otherwise, not transmitting the shunted data to the shunting node device. The data shunting method provided in the embodiments of the present invention enables the data transmission device to provide the shunting node device with an appropriate shunted data rate.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: April 21, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhenzhen Cao, Yi Jiang, Wei Quan, Yu Wang, Xiaolong Guo, Qufang Huang
  • Patent number: 10629650
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
  • Publication number: 20200117574
    Abstract: Embodiments of the present disclosure relate to a method, device and computer program product for software bug verification. In one embodiment, the method includes determining a test action for verification of a software bug to be verified based on an identification of the software bug. The method further includes determining similarities between the test action and a plurality of historical test actions. The method further includes in response to a similarity between the test action and at least one of the plurality of historical test actions exceeding a threshold similarity, associating the test action with a code fragment category associated with the at least one historical test action. The method further includes verifying the software bug by running one code fragment in the code fragment category.
    Type: Application
    Filed: February 25, 2019
    Publication date: April 16, 2020
    Inventors: Fei Peng, Yi Jiang, Zhongyi Zhou
  • Patent number: 10608321
    Abstract: An electronic device may include a substrate and a conductive layer on the substrate. The conductive layer may be patterned to form a first region and a second region that surrounds and defines the shape of the first region. The first region may be formed from a continuous portion of the conductive layer. The second region may include a grid of openings that divides the conductive layer into an array of patches. The first region may form an antenna resonating element for an antenna. The second region may block antenna currents from the antenna resonating element and may be transparent to radio-frequency electromagnetic waves. The openings may have a width that is too narrow to be discerned by the human eye. This may configure the first and second regions to appear as a single continuous conductive layer despite the fact that an antenna resonating element is formed therein.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: March 31, 2020
    Assignee: Apple Inc.
    Inventors: Yi Jiang, Jiangfeng Wu, Lijun Zhang, Siwen Yong, Mattia Pascolini
  • Publication number: 20200097102
    Abstract: A computer stylus may be provided that includes an elongated body with a tip and an opposing end coupled together by a shaft that includes a metal tube. The stylus may include a substrate at the end of the elongated body and conductive traces on the substrate. The conductive traces on the substrate may form an antenna ground, an antenna resonating element arm, and a return path. The antenna resonating element arm may be a helical structure that wraps around the substrate. The antenna ground formed from the conductive traces may be coupled to the metal tube using an intermediate metal layer. A cap structure formed at the opposing end and over the substrate may be interposed between the conductive traces and adhesive to protect the conductive traces from the adhesive. A metal portion of the cap structure may serve as an antenna signal reflector.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Lu Zhang, Yi Jiang, Mattia Pascolini
  • Patent number: 10593728
    Abstract: Integrated circuits and methods for fabricating magnetic tunnel junction (MTJ) structures and integrated circuits are provided. An exemplary method for fabricating an integrated circuit including a magnetic tunnel junction (MTJ) structure includes forming magnetic tunnel junction (MTJ) layers over a substrate. Further, the method includes forming a conductive pillar over the MTJ layers, wherein the conductive pillar is formed with an uppermost surface, and wherein the uppermost surface is not planarized. Also, the method includes etching the MTJ layers to form a pillar structure from portions of the MTJ layers underlying the conductive pillar.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Patent number: 10594028
    Abstract: An electronic device may be provided with a phased antenna array for conveying millimeter wave signals. The array may be mounted to a substrate that includes transmission line layers having a first dielectric permittivity and antenna layers having a second dielectric permittivity that is less than the first dielectric permittivity. A ground plane may be interposed between the antenna layers and the transmission line layers. The array may be mounted to the antenna layers and transceiver circuitry may be mounted to the transmission line layers. Transmission line traces may be formed on the transmission line layers. The relatively high permittivity of the first set of dielectric layers may allow the transmission line traces to be routed relatively close together with minimal electromagnetic interference. The relatively low permittivity of the second set of dielectric layers may allow the array to operate with satisfactory antenna efficiency, gain, and bandwidth.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: March 17, 2020
    Assignee: Apple Inc.
    Inventors: Siwen Yong, Yi Jiang, Jiangfeng Wu, Lijun Zhang, Mattia Pascolini