Patents by Inventor Yi Jing

Yi Jing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF TREATING SUSPENDED SOLIDS AND HEAVY METAL IONS IN SEWAGE
    Publication number: 20160101999
    Abstract: A method of treating suspended solids and heavy metal ions in sewage includes (step 1) adding an iron sulfate reagent to a portion of sewage to be treated such that suspended solids therein undergo preliminary precipitation, and then separating the portion of sewage into primarily treated sewage with low turbidity and low density sludge (LDS); (step 2) filling a tank with the LDS, wherein the tank comprises a first inlet and a first outlet above the first inlet; and (step 3) conveying the other portion of sewage to be treated or the preliminarily treated sewage to the tank through the first inlet such that the sewage percolates though the LDS in the tank to fluidize the LDS and bind the suspended solid to the LDS, and in consequence, after percolating through the sludge, the treated sewage exits the tank through the outlet effluent.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 14, 2016
    Inventors: CHUN-PING HUANG, YI-JING LI, YEN-NUNG LAI
  • CMOS Devices with Reduced Leakage and Methods of Forming the Same
    Publication number: 20160086862
    Abstract: A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a (551) surface plane of the second semiconductor layer.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 24, 2016
    Inventors: Chih-Hsin Ko, Cheng-Hsien Wu, Clement Hsingjen Wann, Yi-Jing Lee
  • Structure and method for semiconductor device
    Patent number: 9287382
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
  • Structure and method and FinFET device
    Patent number: 9276117
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes The device includes a strain-relaxed buffer (SRB) stack over a substrate, a first fin structure disposed over the SRB stack and a liner layer extending along the portion of the second SRB layer and the first semiconductor material layer of the first fin structure.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Pang-Yen Tsai, Tze-Liang Lee
  • Structure and Method and FinFET Device
    Publication number: 20160056277
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes The device includes a strain-relaxed buffer (SRB) stack over a substrate, a first fin structure disposed over the SRB stack and a liner layer extending along the portion of the second SRB layer and the first semiconductor material layer of the first fin structure.
    Type: Application
    Filed: August 19, 2014
    Publication date: February 25, 2016
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Pang-Yen Tsai, Tze-Liang Lee
  • Source/drain structures and methods of forming same
    Patent number: 9269777
    Abstract: The present disclosure provides a semiconductor device including a gate stack disposed over a substrate, a source/drain (S/D) feature at least partially embedded within the substrate adjacent the gate stack. The S/D feature includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer. The second semiconductor material layer is different to the first semiconductor material layer. The S/D also includes a third semiconductor material layer disposed over the second semiconductor material layer, which includes a tin (Sn) material.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
  • Supercontinuum generation system
    Patent number: 9256114
    Abstract: A supercontinuum generation system comprises a noise-like pulse fiber laser structure, an amplification unit and a broadening medium. The noise-like pulse fiber laser structure generates at lease one noise-like pulse of the wavelength less than 1300 nm. The amplification unit includes a gain fiber with which the noise-like pulse is coupled. The broadening medium is coupled with the gain fiber. A supercontinuum is generated when the noise-like pulse is amplified by the amplification unit and broadened in spectrum by the broadening medium.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: February 9, 2016
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Ci-Ling Pan, Alexey Zaytsev, Chih-Hsuan Lin, Yi-Jing You
  • Source/Drain Structures and Methods of Forming Same
    Publication number: 20160027877
    Abstract: The present disclosure provides a semiconductor device including a gate stack disposed over a substrate, a source/drain (S/D) feature at least partially embedded within the substrate adjacent the gate stack. The S/D feature includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer. The second semiconductor material layer is different to the first semiconductor material layer. The S/D also includes a third semiconductor material layer disposed over the second semiconductor material layer, which includes a tin (Sn) material.
    Type: Application
    Filed: July 23, 2014
    Publication date: January 28, 2016
    Inventors: Yi-Jing Lee, KUN-MU LI, CHII-HORNG LI, TZE-LiANG LEE
  • Process for preparation of roflumilast
    Patent number: 9233925
    Abstract: The present invention provides novel processes for the preparation of N-substituted benzamides having the formula VIc: In some embodiments, the invention provides a process for preparation of roflumilast and other pharmaceutically active species. Novel compounds, including intermediates for the synthesis of roflumilast, are also provided.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: January 12, 2016
    Assignee: ScinoPharm (Changshu) Pharmaceuticals, Ltd.
    Inventors: Yi-Jing Chen, Stanislaw Pikul, Shen-Chun Kuo, Guo-dong Chu
  • Apparatus and Method for FinFETs
    Publication number: 20150380527
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • FinFETs with Strained Well Regions
    Publication number: 20150380528
    Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: Yi-Jing Lee, Chi-Wen Liu, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • CMOS devices with reduced leakage and methods of forming the same
    Patent number: 9224734
    Abstract: A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a (551) surface plane of the second semiconductor layer.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Display method and portable device
    Patent number: 9201576
    Abstract: A display method and a portable device are provided. The portable device has a touch screen, and a plurality of application programs is installed in the portable device. The touch screen displays a menu interface and an object corresponding to each application program. When the object corresponding to each application program is displayed, obtain a display format supported by the application program, and determine whether the display format supported by the application program matches a first display format of the touch screen of the portable device. When the display format supported by the application program does not match the first display format of the touch screen, a first annotation message is shown on the object corresponding to the application program.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: December 1, 2015
    Assignee: ASUSTeK COMPUTER INC.
    Inventor: Yi-Jing Chen
  • Methods for forming semiconductor regions in trenches
    Patent number: 9196709
    Abstract: A method includes recessing a portion of a semiconductor substrate between opposite isolation regions to form a recess. After the step of recessing, the portion of the semiconductor substrate includes a top surface. The top surface includes a flat surface, and a slant surface having a (111) surface plane. The slant surface has a bottom edge connected to the flat surface, and a top edge connected to one of the isolation regions. The method further includes performing an epitaxy to grow a semiconductor material in the recess, wherein the semiconductor material is grown from the flat surface and the slant surface, and performing an annealing on the semiconductor material.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Brush Assembly
    Publication number: 20150326099
    Abstract: An electric power steering assembly includes a motor which includes a brush assembly. The brush assembly includes a brush base, a plurality of brush units and a plurality of fixing units for fixing the brush units to the brush base. The brush unit includes a brush, a guide rail and a spring. The rail includes two guiding arms, a closed end interconnecting the guiding arms and wings extending from free ends of the guiding arms. Grooves in the brush receive the guiding arms. The fixing unit includes a first fixture and a second fixture. The closed end of the guide rail engages the first fixture. The second fixture includes two columns spaced from each other. Each column defines a slot in a top end. Protrusions extend from a side of each slot to lock the wings in the slots.
    Type: Application
    Filed: May 6, 2015
    Publication date: November 12, 2015
    Inventors: Rui Feng QIN, Yi JING, Hai Feng SHI
  • Methods for Forming Semiconductor Regions in Trenches
    Publication number: 20150318382
    Abstract: A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate. The portion of the semiconductor substrate has a (111) surface and a bottom surface. The (111) surface is slanted and has a top edge and a bottom edge. The bottom surface is parallel to a top surface of the insulation regions, and is connected to the bottom edge. A semiconductor region overlaps the portion of the semiconductor substrate, wherein the semiconductor region includes a second semiconductor material different from the first semiconductor material. The top edge and the bottom edge of the (111) surface are at a first depth and a second depth, respectively, relative to a top surface of the semiconductor region. A ratio of the first depth to the second depth is smaller than about 0.6.
    Type: Application
    Filed: July 15, 2015
    Publication date: November 5, 2015
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Negative-type photoresist composition for thick film and use thereof
    Patent number: 9170491
    Abstract: The present invention relates to a negative-type photoresist composition for thick film, comprising: (A) 20 to 50 wt % of an alkali-soluble resin which is polymerized from a plurality of kinds of monomers, wherein the monomers includes compounds represented by formulas (1A) and (1B), and based on the weight ratio of the monomers to the alkali-soluble resin, the sum of the formula (1A) compound and the formula (1B) compound are 20 to 60%, and X of the formula (1A) and (1B) may be independently H, methyl or ethyl. (B) 10 to 30 wt % of crosslinker which can be a bisphenol fluorene derivative monomer having at least one ethylenically unsaturated double bond; (C) 5 to 15 wt % of photo initiator; and (D) residual solvent. The present invention also relates to use of the above-mentioned negative-type photoresist compound for thick film.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: October 27, 2015
    Assignee: EVERLIGHT CHEMICAL INDUSTRIAL CORPORATION
    Inventors: Yi Jing Chen, Nai Tien Chou, Hsin Yi Huang, Yen-Cheng Li
  • MARK SEGMENTATION METHOD AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE APPLYING THE SAME
    Publication number: 20150294058
    Abstract: In this disclosure, a mark segmentation method and a method for manufacturing a semiconductor structure applying the same are provided. The mark segmentation method comprises the following steps. First, a plurality of segments having a width WS and separated from each other by a space SS formed on a substrate are identified by a processor. Thereafter, a plurality of marks are set over the segments by the processor. This step comprises: (1) adjusting a width WM of each one of the marks being equal to m(WS+SS)+WS or m(WS+SS)+SS by the processor, wherein m is an integer; and (2) adjusting a space SM of adjacent two of the marks by the processor such that WM+SM=n(WS+SS), wherein n is an integer.
    Type: Application
    Filed: May 15, 2014
    Publication date: October 15, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Ying Huang, Jen-Hsiu Li, Mei-Chen Chen, Ya-Ling Chen, Yi-Jing Wang, Chi-Ming Huang
  • FinFETs with strained well regions
    Patent number: 9159824
    Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Chi-Wen Liu, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Apparatus and method for FinFETs
    Patent number: 9153582
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko