Patents by Inventor Yi Jing

Yi Jing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTENTION ESTIMATION DEVICE AND INTENTION ESTIMATION METHOD
    Publication number: 20190005950
    Abstract: When among simple sentences which are estimation targets for an intention estimator, there is a simple sentence whose intention estimation has failed, a supplementary information estimator estimates supplementary information from the simple sentence by using a supplementary information estimation model stored in a supplementary information estimation model storage. When among the simple sentences which are the estimation targets for the intention estimator, there is a simple sentence from which an imperfect intention estimation result is provided, an intention supplementation unit supplements the imperfect intention estimation result by using the supplementary information estimated by the supplementary information estimator.
    Type: Application
    Filed: March 30, 2016
    Publication date: January 3, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yi JING, Jun ISHII
  • Semiconductor device, static random access memory cell and manufacturing method of semiconductor device
    Patent number: 10170483
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu, Kun-Mu Li
  • FinFET devices with unique fin shape and the fabrication thereof
    Patent number: 10170375
    Abstract: A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • FinFETs with strained well regions
    Patent number: 10164022
    Abstract: A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Chi-Wen Liu
  • FinFETs with strained well regions
    Patent number: 10164023
    Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Chi-Wen Liu, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • FinFETs with strained well regions
    Patent number: 10158015
    Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Semiconductor Device Having Merged Epitaxial Features with Arc-Like Bottom Surface and Method of Making the Same
    Publication number: 20180350687
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • METHOD, MOBILE DEVICE, AND SYSTEM FOR THE MESSAGE TRANSMISSION OF A VULNERABLE ROAD USER
    Publication number: 20180342154
    Abstract: A method, a mobile device, and a system for message transmission of a vulnerable road user (VRU) are provided. The method is adapted to a first mobile device of a first VRU and includes the following steps. Whether there exists a target mobile device within a preset range of the first VRU is determined, where the target mobile device is a mobile device that has already broadcast a personal safety message (PSM). When the target mobile device exists within the preset range, whether to broadcast a first PSM is determined according to a relative distance between the target mobile device and an intersection as well as a relative distance between the target mobile device and the first mobile device. When the target mobile device doesn't exist within the preset range, the first PSM is broadcast.
    Type: Application
    Filed: November 29, 2017
    Publication date: November 29, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Yi-Jing Lee, Po-Chun Kang, Tzu-Hsiang Su, Chia-Tai Tsai
  • FinFET Device Having Flat-Top Epitaxial Features and Method of Making the same
    Publication number: 20180337182
    Abstract: A semiconductor device and method of forming the same are disclosed. The method of forming a semiconductor device includes providing a substrate, an isolation structure over the substrate, and at least two fins extending from the substrate and through the isolation structure; etching the at least two fins, thereby forming at least two trenches; growing first epitaxial features in the at least two trenches; growing second epitaxial features over the first epitaxial features in a first growth condition; and after the second epitaxial features reach a target critical dimension, growing the second epitaxial features in a second growth condition different from the first growth condition.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Inventors: Yi-Jing Lee, Li-Wei Chou, Ming-Hua Yu
  • Semiconductor structure and the manufacturing method thereof
    Patent number: 10115826
    Abstract: The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide. A method for manufacturing the FinFET includes forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation; oxidizing the fin structure and the layer to transform the layer into a first oxide layer; filling insulating material between adjacent fin structures; and etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Apparatus and method for FinFETs
    Patent number: 10084069
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Measuring session initiation protocol (SIP) messaging latency
    Patent number: 10069871
    Abstract: A device may receive a first session initiation protocol (SIP) message from another device, and may determine a first timestamp associated with the first SIP message. The first timestamp may represent a receipt time of the first SIP message by the device. The device may determine a second timestamp associated with a second SIP message. The second timestamp may represent a transmission time of the second SIP message by the device, and may be a response to the first SIP message. The device may determine a device latency value representing a difference between the second timestamp and the first timestamp. The device may provide the second SIP message to the other device at the transmission time. The second SIP message may include the device latency value.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: September 4, 2018
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Yi Jing, Jeffrey R. Evans, Robert P. Faber, Jr., Taral Patel
  • VIRTUAL MACHINE (VM)-TO-VM FLOW CONTROL FOR OVERLAY NETWORKS
    Publication number: 20180232252
    Abstract: In one embodiment, a system includes a processing circuit and logic integrated with and/or executable by the processing circuit that causes the processing circuit to receive a congestion notification message from a first virtual switch of a first server indicating that a first virtual machine (VM) hosted by the first server is overloaded. The logic also causes the processing circuit to advertise a congestion status of the first VM in a congestion status message to one or more virtual switches in a network in response to receiving the congestion notification message. Moreover, the logic causes the processing circuit to cause all virtual switches in the network except for the first virtual switch to stop sending traffic destined for the first VM while the first VM is overloaded without restricting sending traffic that is destined for other VMs hosted by the first server.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 16, 2018
    Inventors: Liang Rong, Gang Tang, Zi Jin Tao, Ming Shuang Xian, Yi Jing Zhu
  • Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same
    Patent number: 10049936
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • Device and method for understanding user intent
    Patent number: 10037758
    Abstract: A voice recognizer 3 generates plural voice recognition results from one input speech 2. For each of the voice recognition results, an intent understanding processor 7 estimates an intent to thereby output one or more candidates of intent understanding results and scores of them. A weight calculator 11 calculates standby weights using setting information 9 of a control target apparatus. An intent understanding corrector 12 corrects the scores of the candidates of intent understanding result, using the standby weights, to thereby calculate their final scores, and then selects one from among the candidates of intent understanding result, as an intent understanding result 13, on the basis of the final scores.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 31, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yi Jing, Yoichi Fujii, Jun Ishii
  • Virtual machine (VM)-to-VM flow control for overlay networks
    Patent number: 10025609
    Abstract: In one embodiment, a method includes receiving, using a controller, a congestion notification message from a first virtual switch of a first server indicating that a first virtual machine (VM) hosted by the first server is overloaded, and advertising, using the controller, a congestion status of the first VM to one or more virtual switches in a network using a congestion status message in response to receiving the congestion notification message. In another embodiment, a method includes receiving, using a first virtual switch of a first server, a congestion status message from a controller indicating that a second VM hosted by a second server is overloaded, and stopping traffic that is destined for the second VM from being sent in response to receiving the congestion status message from the controller without restricting sending traffic that is destined for other VMs hosted by the second server.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Liang Rong, Gang Tang, Zi Jin Tao, Ming Shuang Xian, Yi Jing Zhu
  • Walking trainer
    Patent number: 10022587
    Abstract: A walking trainer includes a linear transmission unit including two carriages, and two pedal units each including a pedal holder, which includes a bottom frame carried on one respective carriage, upright posts mounted at the bottom frame and a top block mounted on and movable up and down along the upright posts, a rotary shaft mounted in the top block in a direction perpendicular to the upright posts and a pedal mounted on the rotary shaft and biasable with the rotary shaft relative to the pedal holder. Thus, the pedals of the pedal units can be moved with the respective carriages linearly and alternatively back and forth, on the other hand, and can also be moved with the associating top blocks up and down and biased with the respective rotary shafts relative to the respective pedal holders to simulate the walking gait path.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: July 17, 2018
    Assignee: HIWIN TECHNOLOGIES CORP.
    Inventors: Yi-Jing Wu, Wen-Bin Lin
  • DIRECT EMITTING LED ILLUMINATION MODULE FOR ELIMINATING CHROMATIC DISPERSION
    Publication number: 20180187863
    Abstract: A direct emitting LED illumination module for eliminating chromatic dispersion improves a vehicular LED lamp to comply with related regulations. The LED illumination module includes a LED light source and a plano-convex lens. The LED light source is located at the focus of the plano-convex lens. The LED light source emits light to the plane of the plano-convex lens, and the light exits from the convex surface of the plano-convex lens. The plano-convex lens focuses the light to form a desirable light pattern. Besides, the plane of the plano-convex lens has a microstructure thereon to suppress the angular correlated color temperature deviation of the light pattern and eliminate chromatic dispersion.
    Type: Application
    Filed: October 19, 2017
    Publication date: July 5, 2018
    Inventors: SHENG-HUA YANG, TAI-KU LAI, PIN-CHU CHEN, YI-JING HUO
  • SEMICONDUCTOR DEVICE HAVING MERGED EPITAXIAL FEATURES WITH ARC-LIKE BOTTOM SURFACE AND METHOD OF MAKING THE SAME
    Publication number: 20180174912
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.
    Type: Application
    Filed: May 15, 2017
    Publication date: June 21, 2018
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF
    Publication number: 20180175031
    Abstract: An integrated circuit includes first and second semiconductor fins, first and second epitaxy structures, and first and second dielectric fin sidewall structures. The first and second epitaxy structures are respectively on the first and second semiconductor fins. The first epitaxy structure and the second epitaxy structure are merged together. The first and second dielectric fin sidewall structures are respectively on opposite first and second sidewalls of the first epitaxy structure. The first sidewall of the first epitaxy structure faces the second epitaxy structure. The first dielectric fin sidewall structure is shorter than the second dielectric fin sidewall structure.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 21, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing LEE, Kun-Mu LI, Ming-Hua YU, Tsz-Mei KWOK