Patents by Inventor Yi Kao

Yi Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230268426
    Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 24, 2023
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11721699
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11715637
    Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
  • Patent number: 11710782
    Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11705327
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Publication number: 20230218207
    Abstract: A substance concentration measuring device, for measuring a substance concentration for a target substance in blood of a subject, comprising: a processing circuit; and a plurality of electrodes. At least two of the electrodes touches the subject when the subject wears the substance concentration measuring device, thereby the processing circuit can acquire at least one physiological signal caused by an eye of the subject. The processing circuit computes a voltage value or a voltage difference of the physiological signal, and computes the substance concentration according to the voltage value or the voltage difference. A human condition monitoring system comprising the substance concentration measuring device is also disclosed.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 13, 2023
    Applicant: PixArt Imaging Inc.
    Inventors: Chih-Hao Wang, Chien-Yi Kao, Yang-Ming Chou, Shih-Jen Lu, Hsin-Yi Lin
  • Publication number: 20230187265
    Abstract: A method includes etching a semiconductor substrate to form a semiconductor strip and a recess, with a sidewall of the semiconductor strip being exposed to the recess, depositing a dielectric layer into the recess, and depositing a capping layer over the dielectric layer. The capping layer extends into the recess, and comprises silicon oxynitride. The method further includes filling remaining portions of the recess with dielectric materials, performing an anneal process to remove nitrogen from the capping layer, and recessing the dielectric materials, the capping layer, and the dielectric layer. The remaining portions of the dielectric materials, the capping layer, and the dielectric layer form an isolation region. A portion of the semiconductor strip protrudes higher than a top surface of the isolation region to form a semiconductor fin.
    Type: Application
    Filed: April 6, 2022
    Publication date: June 15, 2023
    Inventors: Wan-Yi Kao, ChunYao Wang, Yung-Cheng Lu
  • Patent number: 11670500
    Abstract: A method of descumming a dielectric layer is provided. In an embodiment the dielectric layer is deposited over a substrate, and a photoresist is applied, exposed, and developed after the photoresist has been applied. Once the pattern of the photoresist is transferred to the underlying dielectric layer, a descumming process is performed, wherein the descumming process utilizes a mixture of a carbon-containing precursor, a descumming precursor, and a carrier gas. The mixture is ignited into a treatment plasma, and the treatment plasma is applied to the dielectric layer in order to descum the dielectric layer.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yi Kao, Kuang-Yuan Hsu, Tze-Liang Lee
  • Publication number: 20230154746
    Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the method includes forming a dielectric layer, which includes forming an as deposited layer using an atomic layer deposition process, which includes flowing a silicon source precursor into a process chamber at a first flow rate, flowing a carbon and nitrogen source precursor into the process chamber at a second flow rate, and flowing an oxygen source precursor into the process chamber at a third flow rate. A ratio of the first flow rate to the second flow rate to the third flow rate ranges between about one to one to eight and one to one to twelve, and the as deposited layer has a carbon concentration substantially greater than a nitrogen concentration. The method further includes annealing the as deposited layer in an environment including H2O to form the dielectric layer.
    Type: Application
    Filed: May 25, 2022
    Publication date: May 18, 2023
    Inventors: Wan-Yi KAO, Chunyao WANG, Yung-Cheng LU
  • Publication number: 20230155006
    Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.
    Type: Application
    Filed: May 13, 2022
    Publication date: May 18, 2023
    Inventors: Wan-Yi Kao, Fang-Yi Liao, Shu Ling Liao, Yen-Chun Huang, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11640978
    Abstract: Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Publication number: 20230103640
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventors: Wan-Yi Kao, Yu-Cheng Shiau, Chunyao Wang, Chih-Tang Peng, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20230103071
    Abstract: Provided is a method of purifying a terpenoid amino alcohol derivative, including providing a crude terpenoid amino alcohol derivative; performing an acid/base crystallization process of the crude terpenoid amino alcohol derivative to obtain an organic salt; and reacting the organic salt with NaOH and toluene to obtain a purified terpenoid amino alcohol derivative. Also provided is a method of preparing p-mentha-2,8-diene-1-ol from the purified terpenoid amino alcohol derivative.
    Type: Application
    Filed: September 7, 2021
    Publication date: March 30, 2023
    Applicant: SCI PHARMTECH INC.
    Inventors: Chen-Yi Kao, Feng-Hsu Li
  • Publication number: 20230035349
    Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Inventors: Wan-Yi Kao, Szu-Ping Lee, Che-Hao Chang, Chun-Heng Chen, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20230025396
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor protruding structure over a substrate and surrounding the semiconductor protruding structure with an insulating layer. The method also includes forming a dielectric layer over the insulating layer. The method further includes partially removing the dielectric layer and insulating layer using a planarization process. As a result, topmost surfaces of the semiconductor protruding structure, the insulating layer, and the dielectric layer are substantially level with each other. In addition, the method includes forming a protective layer to cover the topmost surfaces of the dielectric layer. The method includes recessing the insulating layer after the protective layer is formed such that the semiconductor protruding structure and a portion of the dielectric layer protrude from a top surface of a remaining portion of the insulating layer.
    Type: Application
    Filed: March 3, 2022
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi KAO, Che-Hao CHANG, Yung-Cheng LU, Chi On CHUI
  • Patent number: 11549990
    Abstract: A capacity judgment module and a capacity calibration method thereof are disclosed. The capacity judgment module is used to judge a capacity of a battery installed in an electronic device. The capacity judgment module includes a database, a voltage detection module and a processing module. The database is used to store the voltage-capacity comparison curve. The voltage detection module is used to obtain a voltage value interval between a maximum use voltage value and a minimum use voltage value of the electronic device so as to divide the voltage value interval into a plurality of levels.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 10, 2023
    Assignee: Gunitech Corp.
    Inventors: Huan-Ruei Shiu, Chung-Liang Hsu, Ming-Yi Wang, Hsin-Yi Kao
  • Patent number: 11527653
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Yu-Cheng Shiau, Chunyao Wang, Chih-Tang Peng, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11507367
    Abstract: A firmware update method and a firmware update system thereof includes the steps of: executing a setting process, which includes writing a first identification code into a memory module, and setting a firmware update file on a firmware providing end to make the firmware update file include a second firmware image file and a second identification code and executing a determining process, which includes receiving the firmware update file and determining whether the firmware update file conforms to a custom structure according to the first identification code. If it does not, then prohibiting the firmware update image file from updating a computer system, and if it does, replacing a first firmware image file with the second firmware image file and writing the second firmware image file into the memory module of the computer system along with the second identification code.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 22, 2022
    Assignee: Gunitech Corp.
    Inventors: Huan-Ruei Shiu, Hsin-Yi Kao, Chung-Liang Hsu, Xiao-Juan Lin, Ming-Yi Wang
  • Patent number: 11502504
    Abstract: A low voltage control system, a low voltage protection method for an electronic device, and a computer program product thereof are disclosed. The electronic device includes a power supply and a memory. The low voltage protection method for the electronic device includes the following steps: detecting a current voltage of the power supply; determining whether the current voltage is lower than a first voltage threshold; and if the voltage is lower than the first voltage threshold, a control module cutting off multiple access channels.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 15, 2022
    Assignee: Gunitech Corp.
    Inventors: Huan-Ruei Shiu, Hsin-Yi Kao, Chung-Liang Hsu, Xiao-Juan Lin, Ming-Yi Wang
  • Publication number: 20220359729
    Abstract: A method includes forming a fin extending from a substrate; forming an first isolation region along opposing sidewalls of the fin; forming a gate structure over the fin; forming an epitaxial source/drain region in the fin adjacent the gate structure; forming an etch stop layer over the epitaxial source/drain region and over the gate structure; forming a protection layer over the etch stop layer, the protection layer including silicon oxynitride; and forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Wan-Yi Kao, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui