Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: An IC design data base generating method, including: receiving a condition parameter, which comprises a process parameter and an operating parameter range comprising at least one operating parameter; and testing at least one cell according to the process parameter and the operating parameter range to generate a delay value data base. The delay value data base comprises a plurality of delay values, wherein the plurality of delay values for an identical cell correspond to the operating parameter range with an identical type but different value. An IC design method using the delay value data base is also disclosed.

Abstract: A method includes etching a semiconductor substrate to form a trench, and depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle. The dielectric layer extends into the trench. The ALD cycle includes pulsing Hexachlorodisilane (HCD) to the semiconductor substrate, purging the HCD, pulsing triethylamine to the semiconductor substrate, and purging the triethylamine. An anneal process is then performed on the dielectric layer.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: Example methods and systems for routing domain computation are described. In one example, a computer system may assign multiple logical entities with respective routing domain identifiers (IDs) by processing network topology information using multiple compute nodes. In response to detecting a network topology change associated with a particular logical entity, the computer system may determine first state change information identifying a first update to first state information maintained by a first compute node; and second state change information identifying a second update to second state information maintained by a second compute node. Further, the particular logical entity with an updated routing domain ID based on the first state change information and the second state change information. The updated routing domain ID may be used in a communication between a management entity and host(s) supporting the particular logical entity.

Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.

Abstract: A power positioning method and a power positioning device thereof are disclosed. The method comprises the steps of: controlling a device to be measured to transmit a plurality of positioning signals by a plurality of transmission powers; causing a plurality of known location devices to receive the plurality of positioning signals and recording the plurality of positioning signals and a plurality of corresponding receiving time to a database; finding out the known location device with a large signal intensity among the received plurality of positioning signals; taking out a signal intensity-distance function and a signal intensity-distance standard deviation function from the database; and finding out a device location of the device to be measured according to the signal intensity-distance function and the signal intensity-distance standard deviation function.

Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

Abstract: A method includes etching a semiconductor substrate to form a trench, and depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle. The dielectric layer extends into the trench. The ALD cycle includes pulsing Hexachlorodisilane (HCD) to the semiconductor substrate, purging the HCD, pulsing triethylamine to the semiconductor substrate, and purging the triethylamine. An anneal process is then performed on the dielectric layer.

Abstract: A capacity judgment module and a capacity calibration method thereof are disclosed. The capacity judgment module is used to judge a capacity of a battery installed in an electronic device. The capacity judgment module includes a database, a voltage detection module and a processing module. The database is used to store the voltage-capacity comparison curve. The voltage detection module is used to obtain a voltage value interval between a maximum use voltage value and a minimum use voltage value of the electronic device so as to divide the voltage value interval into a plurality of levels.

Abstract: A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.

Abstract: An image calibration method applied to an image calibration device includes comparing a first image with a second image to acquire a first overlapping region of the first image and a second overlapping region of the second image, analyzing color distribution of the first overlapping region to acquire at least one first base color value, analyzing color distribution of the second overlapping region to acquire at least one second base color value, setting a ratio of the at least one first base color value to the at least one second base color value as an luminance compensation value when the at least one first base color value is greater than the at least one second base color value, and utilizing the luminance compensation value to adjust pixels of the second image. The first overlapping region is overlapped with the second overlapping region.

Abstract: An image-capturing device includes a camera module and a controller. The camera module captures an image of an object. The camera module includes a first camera and a second camera. The first camera has a first field of view (FOV) and captures an image in the first FOV, so as to produce a first image. The second camera is adjacent to the first camera and has a second FOV, in which the first FOV is wider than the second FOV. The second camera captures an image in the second FOV, so as to produce a second image. A displayer displays one of the first and second images. When a zoom ratio of the first image increases, the controller selects a display region in the first image according to an object distance, such that the display region is enlarged and then displayed on the displayer.