Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.

Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.

Abstract: A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.

Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: An interaction method and apparatus and an electronic device. The method comprises: displaying a first application interface, wherein the first application interface comprises an interface of a first application; and creating a second application account in the first application interface, wherein the second application account is used for logging in a second application. Therefore, a new interaction mode is provided.

Abstract: Methods and systems of using a trained machine-learning model to perform root cause analysis on a manufacturing process. A pre-trained machine learning model is provided that is trained to predict measurements of non-faulty parts. The pre-trained model is trained on training measurement data regarding physical characteristics of manufactured parts as measured by a plurality of sensors at a plurality of manufacturing stations. With the trained model, then measurement data from the sensors is received regarding the manufactured part and the stations. This new set of measurement data is back propagated through the pre-trained model to determine a magnitude of absolute gradients of the new measurement data. The root cause is then identified based on this magnitude of absolute gradients. In other embodiments the root cause is identified based on losses determined between a set of predicted measurement data of a part using the model, and actual measurement data.

Abstract: A method for manufacturing a memory device is provided. The method includes etching an opening in a first dielectric layer; forming a bottom electrode, a resistance switching element, and a top electrode in the opening in the first dielectric layer; forming a second dielectric layer over the bottom electrode, the resistance switching element, and the top electrode; and forming an electrode via connected to a top surface of the top electrode in the second dielectric layer.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.

Abstract: A method for production analysis includes: receiving production data at a processor from a plurality of tools spatially arranged within a manufacturing facility; creating a hierarchal topology of the data in the processor, wherein each level of the hierarchal topology is based on a different one of a plurality of static parameters that are selected from a list consisting of: a tool identifier, a batch identifier, and a spatial orientation; displaying, at a user interface implemented by the processor, a first analysis of a first level of the hierarchal topology, wherein the analysis contains parameters related to other levels of the hierarchal topology; receiving, via the user interface, a selection by a user of a first parameter displayed on the first analysis; and updating the user interface to display a second analysis of a second level of the hierarchal topology that is related to the first parameter.

Abstract: Provided is a method of producing multiple particulates, the method comprising: (a) dispersing multiple primary particles of an anode active material, having a particle size from 2 nm to 20 ?m, and particles of a polymer foam material, having a particle size from 50 nm to 20 ?m, and an optional adhesive or binder in a liquid medium to form a slurry; and (b) shaping the slurry and removing the liquid medium to form the multiple particulates having a diameter from 100 nm to 50 ?m; wherein at least one of the multiple particulates comprises a polymer foam material having pores and a single or a plurality of the primary particles embedded in or in contact with the polymer foam material, wherein the primary particles have a total solid volume Va, and the pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.

Abstract: Disclosed herein is a flexible sensing interface, comprising: a sensor, comprising: a core; an inner electrode in the form of a conductive material in contact with the core; an inner dielectric material substantially encasing the inner electrode; an outer electrode in the form of a conductive material in contact with the inner dielectric material and in electrical communication with the inner electrode; and an outer dielectric material substantially encasing the outer electrode; wherein the inner dielectric material and the outer dielectric material comprise an elastic material. Also disclosed herein are systems and methods for making and using the same.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.

Abstract: A method for communication within a multicore system which includes a primary programmable logic device (PLD) and a secondary PLD installed respectively on a primary motherboard and a secondary motherboard includes steps of: A) by the primary PLD, determining whether the primary motherboard is connected to the secondary motherboard; B) by the primary PLD, after determining that the primary motherboard is connected to the secondary motherboard, sending a reply-requesting signal to the secondary PLD; C) by the secondary PLD, after receiving the reply-requesting signal, sending a reply signal corresponding to the reply-requesting signal to the primary PLD; D) by the primary PLD, after receiving the reply signal, sending an instruction to the secondary PLD; and E) by the secondary PLD, after receiving the instruction, performing an operation corresponding to the instruction.

Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.

Abstract: A probe card and a manufacturing method of a probe card are provided. The probe card includes a probe head, first and second substrates, an insulating component, and an adhesive member. The second substrate is disposed between the probe head and the first substrate, and is disposed on the first substrate. The second substrate faces the first substrate and includes second contacts. The second contacts are electrically connected to first contacts of the first substrate. The insulating component is disposed between the first substrate and the second substrate, and disposed at an outer side of the second contacts. The adhesive member is disposed on the first substrate, arranged on at least a part of the side surface of the second substrate, and disposed at an outer side of the insulating component.