Patents by Inventor Yi Lin

Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250230851
    Abstract: An apparatus is provided. The apparatus includes an equipment support structure configured to support a semiconductor fabrication component. The apparatus includes a damper assembly configured to resist a lateral force induced by a seismic event to the equipment support structure. The damper assembly includes a gear rack coupled to the equipment support structure. The damper assembly includes a first flywheel assembly including a first mass damper flywheel and a first gear meshed with the gear rack and selectively engaged with the first mass damper flywheel.
    Type: Application
    Filed: January 12, 2024
    Publication date: July 17, 2025
    Inventors: Chen Hao LIAO, Chih-Tsung LEE, Ming-Yi LIN, Cheng-Lung WU, Jiun-Rong PAI
  • Publication number: 20250231974
    Abstract: A method that includes obtaining, from one or more stations, embedding vectors that embed features of the stations, obtaining measurement vectors and associated measurement names, generating a text array of the measurement names utilizing a language model, concatenating the text array and the measurement vector at one or more cross-attention modules configured to encode one or more measurement arrays to one or more latent embedding vectors, generating one or more latent embedding vectors associated with the measurement vector and corresponding measurement names via the cross-attention module and a fixed-size station embedding vector, outputting the latent embeddings; generating a query vector; generating key vectors value vectors utilizing a latent embedding vector; decoding the latent vectors utilizing the key vector and value vector; utilizing the cross attention modules and query vectors, decoding the latent embedding vectors; and output a predication.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 17, 2025
    Inventors: Chen QIU, Wan-Yi LIN, Carlos CUNHA, Jared EVANS
  • Publication number: 20250231797
    Abstract: A task scheduling method includes retrieving at least first data generated by monitoring a plurality of processors and second data generated by monitoring a memory subsystem, generating task type data and processor type data according to at least the first data and the second data, dynamically estimating current capacities and maximum capacities of the plurality of processors according to the task type data and the processor type data, generating prediction data according to the task type data, the processor type data, and the current capacities and the maximum capacities of the plurality of processors, scheduling a task according to the task type data, the processor type data, the prediction data, and the current capacities and the maximum capacities of the plurality of processors.
    Type: Application
    Filed: December 17, 2024
    Publication date: July 17, 2025
    Applicant: MEDIATEK INC.
    Inventors: Jia-Ming Chen, Han-Yi Lin, Yu-Pin Chen
  • Patent number: 12361547
    Abstract: A data processing method includes: acquiring an initial sample angiography image set; performing data expansion processing on a first sample angiography image based on physical characteristics of blood vessels at a target site to obtain a processed sample angiography image, performing label conversion processing on a first label based on the physical characteristics of the blood vessels at the target site to obtain a second label of the processed sample angiography image, and adding the processed sample angiography image and the second label to a target sample angiography image set; and training an angiography image recognition model using the initial sample angiography image set and the target sample angiography image set to obtain a trained angiography image recognition model. The performance of the trained angiography image recognition model is improved by increasing the number of samples.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: July 15, 2025
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Dong Wei, Yuexiang Li, Yi Lin, Kai Ma, Yefeng Zheng
  • Publication number: 20250225458
    Abstract: A production scheduling method including: reading work order data and production line status data of each of multiple production lines; identifying a target to-be-scheduled production line according to the production line status data; selecting one or more to-be-scheduled work orders; calculating a production cycle indicator of each of the to-be-scheduled work orders according to a production cycle days, a scheduling date, and a delivery date of the each of the to-be-scheduled work orders; sorting the one or more to-be-scheduled work orders to schedule a first-order target to-be-scheduled work order to the target to-be-scheduled production line for production according to the production cycle indicator, a production process direction, and grade transition cost.
    Type: Application
    Filed: March 31, 2024
    Publication date: July 10, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: I-Chun Sun, Ying-Jung Chen, Yi-Lin Chiang
  • Publication number: 20250226137
    Abstract: A magnetic positioning structure for an expanded device includes a magnetic positioning plate and at least one magnetic conductive element. The magnetic positioning plate with a fixing surface and a mounting surface fixed on a plane includes at least one first magnetic element and an anti-slip sleeve, the first magnetic element is enclosed in the anti-slip sleeve, and the magnetic conductive element is arranged in a housing of the expanded device. In this way, the magnetic conductive element can quickly and temporarily fix the expanded device to the mounting surface of the magnetic positioning plate, and the anti-slip sleeve can prevent displacement of the expanded device. The magnetic positioning structure is applicable to expanded devices such as hubs, notebook docking stations, power banks, etc. to prevent random shaking, keep the operating environment neat without causing wire entanglement or affecting connection angles, thus greatly improving the convenience of use.
    Type: Application
    Filed: August 30, 2024
    Publication date: July 10, 2025
    Inventors: CHUNG-YING CHANG, HUNG-YI LIN, ZHENG-YI WU
  • Publication number: 20250225779
    Abstract: A method and system for training a target neural network using a foundation model having a source neural network that has been pre-trained to operate on a source modality. Inputting source data to the foundation model. The source neural network of the foundation model having at least one source encoder having a source weights which has been pre-trained to compute source features which are computable within the source data of the source modality. Inputting target data to a target neural network operating on a target modality. The target neural network including at least one target encoder having target weights for computing target features within the target data of the target modality. Training the target weight by pairing the target data with the source data and freezing the source weights of the source neural network for a pre-determined epoch.
    Type: Application
    Filed: January 5, 2024
    Publication date: July 10, 2025
    Inventors: Kilian RAMBACH, Joao SEMEDO, Bingqing CHEN, Marcus PEREIRA, Wan-Yi LIN, Csaba DOMOKOS, Yuri FELDMAN, Mariia PUSHKAREVA
  • Patent number: 12354122
    Abstract: A golden path search method for manufacturing process provides a two-phase process to search for a golden path. A first phase step of the two-phase process includes preparing a search model based on a search algorithm, and selecting a plurality of key process stages of a plurality of process stages by feeding sets of final inspection values and the production paths of the workpieces into the searching model, and then generating a plurality of key paths according to the key process stages. A second phase step of the two-phase process includes building a plurality of prediction models of the key paths according to the production paths and the sets of final inspection values, and predicting a plurality of yield rates corresponding to the key paths according to the prediction models, and then searching for the golden path of the key paths according to the yield rates.
    Type: Grant
    Filed: October 23, 2022
    Date of Patent: July 8, 2025
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Chin-Yi Lin, Fan-Tien Cheng, Ching-Kang Ing, Yu-Ming Hsieh, Po-Hsiang Peng
  • Patent number: 12354300
    Abstract: Provided are systems and methods that invert a trained NeRF model, which stores the structure of a scene or object, to estimate the 6D pose from an image taken with a novel view. 6D pose estimation has a wide range of applications, including visual localization and object pose estimation for robot manipulation.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: July 8, 2025
    Assignee: GOOGLE LLC
    Inventors: Tsung-Yi Lin, Peter Raymond Florence, Yen-Chen Lin, Jonathan Tilton Barron
  • Publication number: 20250218168
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing multiple computer vision tasks using a shared computer vision neural network. In one aspect, one of the methods includes obtaining an input image; processing the input image and a prompt sequence using a shared computer vision neural network to generate an output sequence that comprises respective token at each of a plurality of time steps, wherein each token is selected from a shared vocabulary of tokens that is shared between the plurality of computer vision tasks, wherein the shared vocabulary comprises (i) a first set of tokens that each represent a respective discrete number from a set of discretized numbers and (ii) a second set of tokens that each represent a natural language text token.
    Type: Application
    Filed: May 19, 2023
    Publication date: July 3, 2025
    Inventors: Ting Chen, David James Fleet, Geoffrey E. Hinton, Yi Li, Saurabh Saxena, Tsung-Yi Lin
  • Publication number: 20250220042
    Abstract: A system includes a controller configured to generate an original patch utilizing Bayesian optimization, output the original patch at a display at a scene and determine if the original patch does not meet a success criteria of the machine-learning model, in response to the original patch not meeting the success criteria, upscaling the patch, decompose the upscaled patch into o components, for each of the components, utilize Bayesian optimization to update one of the components of the upscaled patch and freezing the other components to generate an updated patch, in response to the updated patch meeting the success criteria, output the updated upscaled patch, and in response to the updated upscaled patch not meeting the success criteria, iteratively update the unfrozen components and determine if the success criteria is met and if not met, unfreeze the frozen components and iteratively update the unfrozen components until the success criteria is met.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: Jianghong Shi, Devin T. Willmott, Wan-Yi Lin, Filipe J. Cabrita Condessa, João D. Semedo
  • Publication number: 20250217494
    Abstract: A computer-implemented method for attacking a machine-learning model, comprising establishing a connection between a processor that is utilizing the machine-learning model, wherein the processor is in communication with a sensor located in a physical scene, outputting on a display device in the physical scene, an adversarial pattern, wherein the display device including the adversarial pattern is located in a sensor range of the sensor, obtaining, from the machine-learning model, a classification associated with the physical scene that includes the adversarial pattern, determining if a target classification has been met with a classification output from the machine-learning model, and in response to the target classification not being met, output additional adversarial patterns at the display device and repeat steps until the target classification has been met.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: Monikasrivyshnavi Nagalla, João D. Semedo, Wan-Yi Lin, FILIPE J. CABRITA CONDESSA
  • Publication number: 20250217493
    Abstract: A system includes a machine learning network input interface configured to receive input data from a sensor, one or more processors collectively programmed to receive an input data from the sensor, wherein the input data is indicative of image of a scene that includes a perturbation from a black-box attack with a physical perturbation at the scene, display an adversarial pattern at the scene, determine an objective function utilizing at least the adversarial pattern and a target classification of the machine-learning network, randomly select a plurality of data points associated with the adversarial pattern and the objective function, wherein the data points are associated with a number of queries of the objective function, obtain a machine-learning model output utilizing the data points displayed in the scene, and in response to meeting a criteria associated with the adversarial pattern and model output, identify a successful attack pattern.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: Jianghong Shi, Devin T. Willmott, Wan-Yi Lin, FILIPE J. CABRITA CONDESSA, Bingqing Chen, João D. Semedo
  • Publication number: 20250217569
    Abstract: A method of extracting parasitic parameters of a 3D IC, including steps of merging respective layouts of multiple dies and backside layout of a 3D IC into a common layout, establishing a common LVS file and a common LPE file for those dies and backside layout based on the common layout, establishing respective LVS files and respective LPE files for every die based on the respective layouts, creating a common netlist from the common LVS file and common LPE file, creating corresponding respective netlists from the respective LVS files and respective LPE files, merging the common netlist and respective netlists into a netlist, and extracting common parasitic parameters of the dies from the netlist.
    Type: Application
    Filed: January 29, 2024
    Publication date: July 3, 2025
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Chih-Yueh Lin, Chun-Yi Lin, Yun-Chi Chiu, Shang-Yu Liu, Yi-Chien Lai, Hsin-Yao Wang, Tsan-Tang Chen, Yen-Hsueh Huang
  • Publication number: 20250218940
    Abstract: A method of fabricating a semiconductor structure provided herein includes providing a thick-metal density range for a model structure, wherein the model structure includes a wafer substrate, and layers of metal patterns stacking on the wafer substrate; modifying the thick-metal density range to constrain a warpage range of the model structure toward a target range of warpage; and fabricating the semiconductor structure by forming the layers of metal patterns on the wafer substrate, wherein a thick-metal layer among the layers of metal patterns is formed based on the modified thick-metal density range, and a thickness of the thick-metal layer is twice or more of a thickness of one of the layers of metal patterns next to the thick-metal layer. A semiconductor structure fabricating by using the above method is further provided.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Chang, Cheng-Hsien WU, Man-Yun WU, Yu-Bey Wu, Wen-Chiung Tu, Chen-Chiu Huang, Dian-Hau Chen, Chung-Yi Lin, Ching-Feng Sung, Hsiu-Chia Kuo
  • Patent number: 12340158
    Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.
    Type: Grant
    Filed: January 4, 2024
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
  • Publication number: 20250203756
    Abstract: A circuit board module capable of suppressing common mode noise includes a circuit board, and a first circuit and a second circuit that are disposed on the circuit board. The circuit board includes an insulating substrate, and a plurality of metal layers. The metal layers are disposed in the insulating substrate, are spaced apart from each other, and include a first metal layer and a second metal layer. The metal layers are formed to include a plurality of conducting lines. The conducting lines cooperatively form a common mode choke structure in which the conducting lines extend in a spiral pattern, so that each of the conducting lines has a spiral winding segment in the spiral pattern. In the spiral pattern, a mutual inductance coupling coefficient between the spiral winding segments of two adjacent ones of the conducting lines is greater than 0.3.
    Type: Application
    Filed: December 11, 2024
    Publication date: June 19, 2025
    Inventors: Yang-Chih HUANG, Chin-Yi LIN
  • Patent number: 12334489
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: January 29, 2024
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Patent number: 12333260
    Abstract: A method, computer system, and a computer program product for task assistance is provided. The present invention may include acquiring a request expression input by a user. The present invention may include identifying a request intent associated with a task based on the request expression. The present invention may include determining a response script corresponding to the request intent. The present invention may include executing the response script to complete the task and presenting the process of running the task in a user-interface (UI).
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: June 17, 2025
    Assignee: International Business Machines Corporation
    Inventors: Jin Shi, Chih-Yuan Lin, Shu-Chih Chen, Chao Yuan Huang, Pei-Yi Lin
  • Publication number: 20250190005
    Abstract: A current driver having an input channel and an output channel includes a current source, a current mirror, an output enable switch and a control circuit. The current source is deployed in the input channel. The current mirror is deployed between the input channel and the output channel and coupled to the current source. The output enable switch is deployed in the output channel and coupled to the current mirror. The control circuit is coupled between the input channel and the output channel, to form a feedback loop through the input channel.
    Type: Application
    Filed: September 11, 2024
    Publication date: June 12, 2025
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Ren-Chieh Yang, Jui-Chan Chang, Jin-Yi Lin, Jhih-Siou Cheng