Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.

Abstract: A probe card and a manufacturing method of a probe card are provided. The probe card includes a probe head, first and second substrates, an insulating component, and an adhesive member. The second substrate is disposed between the probe head and the first substrate, and is disposed on the first substrate. The second substrate faces the first substrate and includes second contacts. The second contacts are electrically connected to first contacts of the first substrate. The insulating component is disposed between the first substrate and the second substrate, and disposed at an outer side of the second contacts. The adhesive member is disposed on the first substrate, arranged on at least a part of the side surface of the second substrate, and disposed at an outer side of the insulating component.

Abstract: A thick document conveying device includes a paper pickup mechanism. The paper pickup mechanism has a pick roller base, a pick roller axle, a pick roller, a switching assembly, a first universal coupling, a driving mechanism, a second universal coupling, a bearing and a gear. The pick roller axle and the pick roller are located in the pick roller base. The switching assembly is located under the pick roller base. The first universal coupling is connected to the pick roller axle. The driving mechanism is sleeved on the first universal coupling. The second universal coupling is connected to the driving mechanism. The bearing is connected to the driving mechanism. The gear is connected to the bearing. As described above, both a thick document and a thin document can be adapted.

Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

Abstract: An uplink multi-user multi-input multi-output establishment method includes broadcasting, by a network side device, an uplink data sending announcement; receiving buffer information sent by a terminal that needs to send data, where the buffer information includes at least a sending level and a data sending length of to-be-sent data; determining, according to the buffer information, scheduling information for establishing uplink multi-user multi-input multi-output; and sending, to a terminal that is allowed to send data and selected from the terminal that needs to send data, a clear to send frame that carries the scheduling information, so that the terminal that is allowed to send data sends the to-be-sent data according to the scheduling information. The embodiments of the present disclosure effectively implement uplink multi-user multi-input multi-output establishment, so that signaling interworking is reduced, resource overheads are reduced, and data sending efficiency is improved.

Abstract: One or more electronic devices that are mounted on a substrate, including at least one cooling plate in contact with the one or more electronic devices, are encapsulated. The substrate is clamped between a first mold half and a second mold half which define a molding cavity for molding the one or more electronic devices. A cavity insert movably located in the first mold half is projected into the cavity in order to contact and apply a sealing pressure onto the at least one cooling plate. After introducing a molding compound into the cavity at a first fill pressure, the molding compound in the cavity is packed by applying a second fill pressure which is higher than the first fill pressure. During this time, the sealing pressure is maintained at values that are higher than the first fill pressure and the second fill pressure.

Abstract: A method for determining a standard depth value of a marker includes obtaining a maximum depth value of the marker. A reference depth value of the marker is obtained based on a depth image of the marker, and a Z-axis coordinate value of the marker is obtained based on a color image of the marker. When the reference depth value and the Z-axis coordinate value are both less than the maximum depth value, and a difference between the reference depth value and the Z-axis coordinate value is not greater than 0, the depth reference value is set as the standard depth value of the marker; and when the difference is greater than 0, the Z-axis coordinate value is set as the standard depth value of the marker.

Abstract: A display driver circuit for controlling a display panel having a plurality of light-emission diode (LED) strings includes a plurality of current regulators and a control circuit. Each of the plurality of current regulators is configured to control one of the plurality of LED strings. The control circuit, coupled to the plurality of current regulators, is configured to generate a plurality of pulses in a plurality of pulse width modulation (PWM) signals and output each of the plurality of PWM signals to a respective current regulator among the plurality of current regulators. Wherein, the plurality of pulses are scrambled.

Abstract: A control method of a driving mechanism is provided, including: the driving mechanism provides a first electrical signal from a control assembly to the driving mechanism to move the movable portion into an initial position relative to the fixed portion, wherein the control assembly includes a control unit and a position sensing unit; the status signal of an inertia sensing unit is read; the control unit sends the status signal to the control unit to calculate a target position; the control unit provides a second electrical signal to the driving assembly according to the target position for driving the driving assembly; a position signal is sent from the position sensing unit to the control unit; the control unit provides a third electric signal to the driving assembly to drive the driving assembly according the position signal.

Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A detection method for a malicious domain name in a domain name system (DNS) and a detection device are provided. The method includes: obtaining network connection data of an electronic device; capturing log data related to at least one domain name from the network connection data; analyzing the log data to generate at least one numerical feature related to the at least one domain name; inputting the at least one numerical feature into a multi-type prediction model, which includes a first data model and a second data model; and predicting whether a malicious domain name related to a malware or a phishing website exists in the at least one domain name by the multi-type prediction model according to the at least one numerical feature.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: A fish identification method is provided. The fish identification method includes capturing an image through a processor, wherein the image includes a fish image. The fish identification method includes identifying a plurality of feature points of the fish image through a coordinate detection model and obtaining a plurality of sets of feature-point coordinates. Each of the plurality of sets of feature-point coordinates corresponds to each of the plurality of feature points. The fish identification method further includes calculating a body length or an overall length of the fish image according to the plurality of sets of feature-point coordinates of the image.

Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.