Patents by Inventor Yi-Lin Chuang
Yi-Lin Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104285Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Song LIU, Shih-Yao LIN, Wen-Yuan FANG
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Patent number: 11900037Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: GrantFiled: May 24, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Patent number: 11893334Abstract: A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.Type: GrantFiled: July 27, 2022Date of Patent: February 6, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Shi-Wen Tan, Song Liu, Shih-Yao Lin, Wen-Yuan Fang
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Patent number: 11853675Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.Type: GrantFiled: August 8, 2022Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Shi-Wen Tan, Song Liu, Shih-Yao Lin, Wen-Yuan Fang
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Patent number: 11853681Abstract: A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.Type: GrantFiled: April 16, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching Hsu, Heng-Yi Lin, Yi-Lin Chuang
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Publication number: 20230385520Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Yi-Lin CHUANG, Shih-Yao LIN, Szu-ju HUANG, Yin-An CHEN, Shih Feng HONG
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Publication number: 20230385521Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Yi-Lin CHUANG, Shih-Yao LIN, Szu-ju HUANG, Yin-An CHEN, Shih Feng HONG
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Patent number: 11816417Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: GrantFiled: February 22, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Henry Lin, Szu-ju Huang, Yin-An Chen, Amos Hong
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Publication number: 20230325573Abstract: A method includes providing a placing layout of the integrated circuit; generating a routed layout including a layout region with a systematic design rule check (DRC) violation; and performing a loop when the DRC the systematic DRC violation exists. The loop includes: generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe; extracting features of the placing layout to obtain extracted data; extracting features of the layout region with the systematic DRC violation to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models; and selecting the target placement recipe from a plurality of placement recipes to generate the adjusted routing layout.Type: ApplicationFiled: May 31, 2023Publication date: October 12, 2023Inventors: SHIH-YAO LIN, YI-LIN CHUANG, YIN-AN CHEN, SHIH FENG HONG
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Patent number: 11709987Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.Type: GrantFiled: July 27, 2021Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Yao Lin, Yi-Lin Chuang, Yin-An Chen, Shih Feng Hong
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Publication number: 20230229846Abstract: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.Type: ApplicationFiled: January 23, 2023Publication date: July 20, 2023Inventors: Ching Hsu, Shih-Yao Lin, Yi-Lin Chuang
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Publication number: 20230214575Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Inventors: Yi-Lin Chuang, Szu-ju Huang, Shih-Yao Lin, Shih Feng Hong, Yin-An Chen
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Publication number: 20230153508Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.Type: ApplicationFiled: January 19, 2023Publication date: May 18, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Lin CHUANG, Huang-Yu CHEN, Yun-Han LEE
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Patent number: 11604917Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: GrantFiled: August 9, 2021Date of Patent: March 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Patent number: 11568119Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.Type: GrantFiled: January 17, 2021Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee
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Patent number: 11562118Abstract: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.Type: GrantFiled: January 4, 2021Date of Patent: January 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching Hsu, Shih-Yao Lin, Yi-Lin Chuang
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Publication number: 20220391574Abstract: A system and method for fixing DRC violations includes receiving a layout pattern having a design rule check (DRC) violation therein, determining that the layout pattern is an inlier based upon a comparison of the layout pattern with a plurality of previously analyzed layout patterns. The comparison may be performed by an anomaly detection algorithm. The system and method may also include selecting a recipe from a pool of recipes previously applied to the plurality of previously analyzed layout patterns for fixing the DRC violation in the layout clip upon determining that the layout pattern is an inlier.Type: ApplicationFiled: July 28, 2022Publication date: December 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chen Huang, Heng-Yi Lin, Yi-Lin Chuang
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Publication number: 20220382950Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Song LIU, Shih-Yao LIN, Wen-Yuan FANG
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Publication number: 20220366121Abstract: A method includes the following operations: identifying a layer of a first layout based on a first violation generated on the layer; generating a metal density value associated with the layer; when the metal density value is larger than or equal to a preset value, classifying the first violation into a first class corresponding to routing congestions of the first layout; when the first violation is classified into the first class, assigning, to the first violation, a first operation of a plurality of first pre-stored operations corresponding to the first class; and performing the first operation to the first layout to generate a second layout.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Song LIU, Pei-Pei CHEN, Heng-Yi LIN, Shih-Yao LIN, Chin-Hsien WANG
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Publication number: 20220366118Abstract: A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Song LIU, Shih-Yao LIN, Wen-Yuan FANG