Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.

Abstract: An integrated circuit (IC) semiconductor device has a high oxide definition (OD) density region, a low OD density region adjacent to the high OD density region, and dummy cells in the high OD density region and the low OD density region to smooth a density gradient between the high OD density region and the low OD density region.

Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.

Abstract: A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information.

Abstract: An integrated circuit (IC) semiconductor device has a high oxide definition (OD) density region, a low OD density region adjacent to the high OD density region, and dummy cells in the high OD density region and the low OD density region to smooth a density gradient between the high OD density region and the low OD density region.

Abstract: A method of reducing an oxide definition (OD) density gradient in an integrated circuit (IC) semiconductor device having a placed layout and a set of design rule checking (DRC) rules associated with the placed layout. The method includes computing OD density in insertion regions from OD density information corresponding to the placed layout to identify an OD density gradient. The method further includes selecting and adding dummy cells to at least one insertion region to reduce the OD density gradient.

Abstract: In some embodiments, in a method, a physical netlist of a placed IC chip design is received. The physical netlist comprises a plurality of registers. Timing criticalities of register pairs in the registers are obtained. Weights to the register pairs are assigned based on the timing criticalities of the register pairs. Candidate registers that are in physical vicinity of a first cluster are identified. If a first candidate register in the candidate registers of the first cluster is in a second cluster, selecting the first candidate register as the first register to be added to the first cluster if sum of weights of other candidate registers in register pairs across the boundary of the first cluster and the first candidate register in one or more register pairs across a boundary of the second cluster is optimized.

Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. The layout method can include placing a circuit cell and an inter-layer via together in a first device layer of the IC structure, and placing a metal pattern in a second device layer of the IC structure. The inter-layer via and the metal pattern may be configured to form a direct connection channel for the circuit cell and the metal pattern.

Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.

Abstract: A method of reducing an oxide definition (OD) density gradient in an integrated circuit (IC) semiconductor device having a placed layout and a set of design rule checking (DRC) rules associated with the placed layout. The method includes computing OD density in insertion regions from OD density information corresponding to the placed layout to identify an OD density gradient. The method further includes selecting and adding dummy cells to at least one insertion region to reduce the OD density gradient.

Abstract: In some embodiments, in a method, a physical netlist of a placed IC chip design is received. The physical netlist comprises a plurality of registers. Timing criticalities of register pairs in the registers are obtained. Weights to the register pairs are assigned based on the timing criticalities of the register pairs. Candidate registers that are in physical vicinity of a first cluster are identified. If a first candidate register in the candidate registers of the first cluster is in a second cluster, selecting the first candidate register as the first register to be added to the first cluster if sum of weights of other candidate registers in register pairs across the boundary of the first cluster and the first candidate register in one or more register pairs across a boundary of the second cluster is optimized.

Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.

Abstract: A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information.

Abstract: A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information.

Abstract: In some embodiments, in a method performed by at least one processor, a physical netlist of a placed integrated circuit (IC) chip design is received by the at least one processor. The physical netlist comprises a plurality of registers. Timing criticalities of register pairs in the registers are obtained by the at least one processor. Clusters of the registers are formed by the at least one processor. When forming cluster of the registers, candidate registers that are in physical vicinity of a first cluster are identified, and a first register is selected to be added to the first cluster by giving priority to a candidate register in a register pair across a boundary of the first cluster and with a higher timing criticality over a candidate register located closer to the first cluster. The registers in the same cluster have shorter non-common clock paths than the registers in different clusters.

Abstract: Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.

Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.

Abstract: Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Abstract: Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.