Patents by Inventor Yi-Lin Chuang
Yi-Lin Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11481536Abstract: A method includes the following operations: receiving design rule violations of a first layout; classifying, according to first chip features of the first layout, a first violation of the design rule violations into a first class of predefined classes; generating a first vector array for at least one of the first chip features of the first layout, that is associated with the first violation; selecting, according to the first vector array, first operations from pre-stored operations; generating a second layout based on the first layout and the first operations.Type: GrantFiled: December 8, 2020Date of Patent: October 25, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Song Liu, Pei-Pei Chen, Heng-Yi Lin, Shih-Yao Lin, Chin-Hsien Wang
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Publication number: 20220335197Abstract: A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Inventors: Ching Hsu, Heng-Yi Lin, Yi-Lin Chuang
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Patent number: 11443096Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.Type: GrantFiled: October 15, 2020Date of Patent: September 13, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Shi-Wen Tan, Song Liu, Shih-Yao Lin, Wen-Yuan Fang
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Patent number: 11443097Abstract: A system and method for fixing DRC violations includes receiving a layout pattern having a design rule check (DRC) violation therein, determining that the layout pattern is an inlier based upon a comparison of the layout pattern with a plurality of previously analyzed layout patterns. The comparison may be performed by an anomaly detection algorithm. The system and method may also include selecting a recipe from a pool of recipes previously applied to the plurality of previously analyzed layout patterns for fixing the DRC violation in the layout clip upon determining that the layout pattern is an inlier.Type: GrantFiled: November 24, 2020Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yu-Chen Huang, Heng-Yi Lin, Yi-Lin Chuang
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Publication number: 20220284162Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Publication number: 20220215149Abstract: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.Type: ApplicationFiled: January 4, 2021Publication date: July 7, 2022Inventors: Ching Hsu, Shih-Yao Lin, Yi-Lin Chuang
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Patent number: 11347920Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: GrantFiled: October 21, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-Yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Publication number: 20220164515Abstract: A system and method for fixing DRC violations includes receiving a layout pattern having a design rule check (DRC) violation therein, determining that the layout pattern is an inlier based upon a comparison of the layout pattern with a plurality of previously analyzed layout patterns. The comparison may be performed by an anomaly detection algorithm. The system and method may also include selecting a recipe from a pool of recipes previously applied to the plurality of previously analyzed layout patterns for fixing the DRC violation in the layout clip upon determining that the layout pattern is an inlier.Type: ApplicationFiled: November 24, 2020Publication date: May 26, 2022Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Chen Huang, Heng-Yi Lin, Yi-Lin Chuang
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Publication number: 20220147691Abstract: A method includes the following operations: receiving design rule violations of a first layout; classifying, according to first chip features of the first layout, a first violation of the design rule violations into a first class of predefined classes; generating a first vector array for at least one of the first chip features of the first layout, that is associated with the first violation; selecting, according to the first vector array, first operations from pre-stored operations; generating a second layout based on the first layout and the first operations.Type: ApplicationFiled: December 8, 2020Publication date: May 12, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPNAY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Song LIU, Pei-Pei CHEN, Heng-Yi LIN, Shih-Yao LIN, Chin-Hsien WANG
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Publication number: 20220121798Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Publication number: 20220092248Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.Type: ApplicationFiled: October 15, 2020Publication date: March 24, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Song LIU, Shih-Yao LIN, Wen-Yuan FANG
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Patent number: 11263375Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.Type: GrantFiled: June 30, 2020Date of Patent: March 1, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Shi-Wen Tan, Szu-Ju Huang, Shih-Feng Hong
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Publication number: 20210384119Abstract: A method (of forming a three dimensional integrated circuit (3DIC) structure) includes: forming an interconnection layer including forming a first inter-layer via which connects at a first predetermined location to a first circuit region of a first device layer and which has a footprint that is at least one factor of ten smaller than a footprint of the first circuit region; and forming a first conductive segment in a first metallization layer of a second device layer so as to align with and thereby connect to the first inter-layer via.Type: ApplicationFiled: August 20, 2021Publication date: December 9, 2021Inventors: Yi-Lin CHUANG, Ching-Fang CHEN, Jia-Jye SHEN
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Publication number: 20210365620Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.Type: ApplicationFiled: June 30, 2020Publication date: November 25, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Szu-Ju HUANG, Shih-Feng HONG
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Publication number: 20210365624Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Publication number: 20210357569Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.Type: ApplicationFiled: July 27, 2021Publication date: November 18, 2021Inventors: SHIH-YAO LIN, YI-LIN CHUANG, YIN-AN CHEN, SHIH FENG HONG
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Patent number: 11114376Abstract: A system (including a processor and memory with computer program code) that is configured to execute a method which includes generating the layout diagram including: selecting a circuit cell which includes an active element; bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit; placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram; and placing a metal pattern in a second device layer of the layout diagram; and wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern.Type: GrantFiled: February 14, 2020Date of Patent: September 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lin Chuang, Ching-Fang Chen, Jia-Jye Shen
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Patent number: 11093681Abstract: A method of generating an integrated circuit includes: placing a plurality of electronic components on a layout floor plan to generate a placing layout of the integrated circuit; forming a clock tree upon the placing layout to generate a synthesis layout of the integrated circuit; routing the synthesis layout to generate a routed layout of the integrated circuit; performing a DRC process upon the routed layout to obtain a layout region with a systematic DRC violation; generating a plurality of prediction gains of the layout region according to a plurality of placement recipes respectively; and generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in the plurality of placement recipes.Type: GrantFiled: March 24, 2020Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Yao Lin, Yi-Lin Chuang, Yin-An Chen, Shih Feng Hong
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Patent number: 11087066Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: GrantFiled: September 21, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Publication number: 20210174000Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Inventors: Yi-Lin Chuang, Henry Lin, Szu-ju Huang, Yin-An Chen, Amos Hong