Patents by Inventor Yi Liu

Yi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240205959
    Abstract: Methods and apparatus of enhanced candidate allocation schemes for enhanced PDCCH are disclosed. The method includes: receiving, by a receiver, configurations of a plurality of search space sets that are linked for a Physical Downlink Control Channel (PDCCH) transmission with a plurality of repetitions; wherein the plurality of repetitions of the PDCCH are transmitted on a plurality of candidates; determining, by a processor, according to a priority rule with a predefined granularity, by counting the candidates from the linked search space sets, whether there is sufficient candidate resource available for allocation; and allocating, by the processor, the candidates, upon determining that there is sufficient candidate resource available for allocation.
    Type: Application
    Filed: March 22, 2021
    Publication date: June 20, 2024
    Applicant: Lenovo (Beijing) Limited
    Inventors: Yi Zhang, Chenxi Zhu, Bingchao Liu, Wei Ling, Lingling Xiao
  • Publication number: 20240205737
    Abstract: Systems, apparatuses and methods provide technology that determines that a primary slice of a plurality of slices of a communication network is overloaded. The plurality of slices includes a backup slice. The technology assigns user equipment to operate with the backup slice in response to the primary slice being overloaded. The technology identifies that a trigger has occurred, wherein the trigger is associated with one or more of the user equipment, the backup slice or the primary slice, and re-assigns the user equipment to the primary slice from the backup slice so that the user equipment operates with the primary slice.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Applicant: Meta Platforms, Inc.
    Inventors: Curt Wong, Yi Lu, Jimin Liu
  • Publication number: 20240199332
    Abstract: The invention provides an electronic device and a method for managing a shelf configuration in a warehouse. The method includes the following. A number of aisles is obtained by using a number-of-aisles-optimization-function associated with warehouse-structure-information. A number of turnstiles is obtained by using a number-of-turnstiles-optimization-function associated with the warehouse-structure-information. A commodity placement mode is obtained by using a commodity-score-function associated with order information and commodity information. The number of aisles, the number of turnstiles, and the commodity placement mode are used as a warehouse shelf configuration result.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 20, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Li-Yi Liu, Po-Yu Huang, Wei-Kang Liang
  • Publication number: 20240206118
    Abstract: Heat-and-cold recovery system based on liquid cooling data center (energy storage power station) includes high-temperature heat pump, pressure-less heat-storage tank, pressurized heat-storage tank, absorption-type water chiller group, compression-type water chiller group, water cold-storage tank, and PCM cold-storage tank.
    Type: Application
    Filed: May 15, 2023
    Publication date: June 20, 2024
    Inventors: Ning WANG, Shitong LIU, Lingyun WANG, Yao YAO, Yi SUN, Bin Shen
  • Publication number: 20240205958
    Abstract: A method performed by a network node and a network node is provided. The method includes obtaining interference information for a current cell, the interference information for indicating interference levels at time units of a next period in each interference measurement area of a plurality of interference measurement areas of the current cell, obtaining scheduling priorities of user equipments (UEs) at the time units of the next period according to the interference information and locations of the UEs in the current cell, and performing a scheduling of the UEs in the current cell according to the scheduling priorities.
    Type: Application
    Filed: May 4, 2023
    Publication date: June 20, 2024
    Inventors: Haiyi LIU, Huiyang WANG, Xiaohui LIANG, Jing YUAN, Yi ZHAO, Xiangning LI
  • Publication number: 20240205919
    Abstract: Embodiments of the present disclosure relate to methods and apparatuses for multiple transmit-receive point (M-TRP) based physical uplink shared channel (PUSCH) transmission. According to an embodiment of the present disclosure, a method can include: receiving configuration information of a first sounding reference signal (SRS) resource set and a second SRS resource set for a codebook or non-codebook based PUSCH transmission; receiving a configured (CG) configuration for the PUSCH transmission, wherein the CG configuration includes one or two sets of power control parameters, and each set of power control parameter is associated with one SRS resource set of the first SRS resource set or the second SRS resource set; receiving downlink control information (DCI) scheduling a PUSCH retransmission corresponding to the PUSCH transmission according to the CG configuration; and determining at least one set of power control parameters for the PUSCH retransmission.
    Type: Application
    Filed: August 5, 2021
    Publication date: June 20, 2024
    Inventors: Lingling XIAO, Bingchao LIU, Chenxi ZHU, Wei LING, Yi ZHANG
  • Publication number: 20240204061
    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide methods to reduce the resistance of the work function layer of an electronic device, as well as using a low resistivity metal for filling the gate.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 20, 2024
    Inventors: Srinivas Gandikota, Yixiong Yang, Yongjing Lin, Tuerxun Ailihumaer, Tengzhou Ma, Yuanhua Zheng, Zhihui Liu, Shih Chung Chen, Janardhan Devrajan, Yi Xu, Yu Lei, Mandyam Sriram
  • Publication number: 20240204398
    Abstract: Apparatuses, methods, and systems are disclosed for controlling a reconfigurable intelligent surface device. One method (500) includes determining (502) a control signal for a reconfigurable intelligent surface device to control a parameter of at least one element of a plurality of elements of the reconfigurable intelligent surface device. The parameter includes information indicating a phase angle. The method (500) includes transmitting (504) the control signal to the reconfigurable intelligent surface device to control the parameter of the at least one element of the reconfigurable intelligent surface device.
    Type: Application
    Filed: April 16, 2021
    Publication date: June 20, 2024
    Inventors: Chenxi Zhu, Bingchao Liu, Yi Zhang
  • Publication number: 20240205432
    Abstract: The technology of this application relates to an encoding method, an encapsulation method, a display method, an apparatus, and an electronic device. The encoding method includes obtaining a to-be-encoded image, determining N encoding scales (N is an integer greater than 1) for the image, determining an encoding parameter corresponding to each of the N encoding scales, to obtain N groups of encoding parameters, and encoding the image N times by using a preset single-scale encoder based on the N groups of encoding parameters to obtain N groups of bitstream data. In this way, the image is encoded to obtain the bitstream data with a small data amount (namely, the bitstream data with a low encoding scale), so that when a network fluctuates, the bitstream data corresponding to the image can arrive at a decoder side with a higher probability, thereby ensuring smoothness of video playing.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 20, 2024
    Inventors: Peiyun DI, Xin LIU, Yi SONG, Xiaoyu YANG, Xuejian GONG
  • Publication number: 20240203907
    Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a
    Type: Application
    Filed: February 29, 2024
    Publication date: June 20, 2024
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 12016221
    Abstract: A display substrate, a method for manufacturing the display substrate and a display device are provided. The display substrate includes a display region and a non-display region surrounding the display region. The display substrate further includes: an organic functional layer including a first portion located in the display region and a second portion located in the non-display region. The second portion is provided with at least one isolation groove, and is partitioned into at least two separate sub-portions by the at least one isolation groove, and the at least two sub-portions are arranged sequentially along a first direction from the display region to a boundary of the display substrate.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 18, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jie Dai, Pengfei Yu, Siyu Wang, Shun Zhang, Yi Zhang, Tingliang Liu, Sen Du, Li Song
  • Patent number: 12011848
    Abstract: A sand spreader includes a sand storage chamber. Two sand discharge ports are disposed below the sand storage chamber, and are an upper-layer staggered sand discharge port and a lower-layer sand pressing plate sand discharge port, respectively. The upper-layer staggered sand discharge port comprises a left side sand discharge plate and a right side sand discharge plate configured to intersect with each other. Horizontal staggered ports are formed in a position at the bottom of the two sand discharge plates, and vertical spacing between the staggered ports is adjustable. Also comprised is the lower-layer sand pressing plate sand discharge port, including left and right side sand pressing plates. Vertical sand discharge ports are disposed between the sand pressing plates on the two sides, and the width of the vertical sand discharge ports is adjustable, so as to further facilitate control over the amount of discharged sand.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 18, 2024
    Assignee: KOCEL INTELLIGENT MACHINERY LIMITED
    Inventors: Rui Ma, Jiejun He, Fan Peng, Yi Liu, Bao Yang, Yunlong Xu, Mengqing Yuan, Tianyang Zhang
  • Patent number: 12012472
    Abstract: A unimodal ethylene-co-1-hexene copolymer that, when in melted form at 190 degrees Celsius, is characterized by a unique melt property space defined by combination of melt elasticity and complex viscosity ratio (shear thinning) properties. A blown film consisting essentially of the unimodal ethylene-co-1-hexene copolymer. A method of synthesizing the unimodal ethylene-co-hexene copolymer. A method of making the blown film. A manufactured article comprising the unimodal ethylene-co-1-hexene copolymer.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 18, 2024
    Assignee: UNIVATION TECHNOLOGIES, LLC
    Inventors: Bo Liu, Yi Zhang, Ayush A. Bafna, Fran├žois Alexandre, Robert N. Reib
  • Patent number: 12015017
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 12014483
    Abstract: Analysis of edge closures of metal surface particles based on a graph structure.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: June 18, 2024
    Assignee: International Business Machines Corporation
    Inventors: Zhong Fang Yuan, Hong Bing Zhang, Tong Liu, Dan Zhang, Yi Chen Zhong, Xu Min
  • Patent number: 12013789
    Abstract: Methods, systems, and devices for flexible information compression at a memory system are described. For example, a memory system may compress information in a change log to reduce the frequency of transfers of one or more mappings between volatile memory and non-volatile memory. The memory system may compress information associated with a sequence of sequentially-indexed addresses by storing the information associated with those addresses at a pair of entries in the change log. The memory system may additionally switch between a first operating mode associated with identifying sequentially-indexed addresses and generating compressed entries, and a second operating mode associated with generating entries of the change log for each address received in commands.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yanming Liu, Zhenzhen Yang, Yi Heng Sun, Junjun Wang
  • Patent number: 12014976
    Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo Lung Pan, Yu-Chia Lai, Teng-Yuan Lo, Mao-Yen Chang, Po-Yuan Teng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
  • Patent number: 12012467
    Abstract: Compounds of formula (I) as inhibitors of DCN1 and compositions containing the same are disclosed. Methods of using the DCN1 inhibitors in the treatment of diseases and conditions wherein inhibition of DCN1 provides a benefit, like oxidative stress-related diseases and conditions, neurodegenerative diseases and conditions, metabolic disorders, and muscular nerve degeneration, also are disclosed.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 18, 2024
    Assignee: REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Shaomeng Wang, Haibin Zhou, Jianfeng Lu, Liu Liu, Yi Sun, Denzil Bernard
  • Patent number: 12014684
    Abstract: Provided is a pixel circuit configured to drive, in an Xth frame period, a light emitting device to emit light. The Xth frame period includes Y data writing stages and Z light emitting stages, in which a yth data writing stage includes a first sub-stage to a third sub-stage. The pixel circuit includes: a driving transistor; a first reset module configured to transmit, in the first sub-stage, a first initialization signal to the driving transistor in response to a first scanning signal; a gating module configured to perform, in the second sub-stage, a threshold compensation on the driving transistor in response to a second scanning signal; and an input module configured to transmit, in the third sub-stage, a data signal to the driving transistor in response to a third scanning signal. X, Y, Z and y are positive integers, y?Y, and Y?Z.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: June 18, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tingliang Liu, Lingtong Li, Huijuan Yang, Xiaoqing Shu, Liheng Wei, Maoying Liao, Yi Zhang, Yixuan Long, Nanhao Chen, Peng Xu
  • Publication number: 20240192456
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Application
    Filed: February 26, 2024
    Publication date: June 13, 2024
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu