Patents by Inventor Yi Lo

Yi Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240160820
    Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).
    Type: Application
    Filed: January 22, 2024
    Publication date: May 16, 2024
    Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu
  • Publication number: 20240154607
    Abstract: Systems, methods, circuits, and apparatus for managing signal transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: one or more target units each configured to receive a signal and a plurality of inverting units arranged on signal paths to the one or more target units. For each of the one or more target units, one or more corresponding inverting units of the plurality of inverting units are configured to invert the signal multiple times along a corresponding signal path to the target unit to cause a signal width of the inverted signal received by the target unit to be substantially identical to a signal width of the signal.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Applicant: Macronix International Co., Ltd.
    Inventors: Wei-Yi Cheng, Su-Chueh Lo
  • Publication number: 20240135078
    Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.
    Type: Application
    Filed: January 4, 2024
    Publication date: April 25, 2024
    Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
  • Publication number: 20240128381
    Abstract: A power diode device includes a substrate. The substrate includes a core layer of a first conductive type, a first diffusion layer of the first conductive type, a second diffusion layer of a second conductive type, and a heavily doped region of the second conductive type. The core layer is located between the first diffusion layer and the second diffusion layer. A thickness of the core layer is greater than that of the second diffusion layer. The heavily doped region is located in the second diffusion layer and extends toward the core layer to form a PN junction between the heavily doped region and the core layer. A method for manufacturing the power diode device is also provided.
    Type: Application
    Filed: June 2, 2023
    Publication date: April 18, 2024
    Inventors: Ching Chiu TSENG, Tzu Yuan LO, Chao Yi CHANG
  • Patent number: 11959956
    Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 11934106
    Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Yen Liu, Hui-Fang Kuo, Chian-Ting Huang, Wei-Cyuan Lo, Yung-Feng Cheng, Chung-Yi Chiu
  • Patent number: 11915636
    Abstract: A gamma voltage generator, a source driver and a display apparatus are provided. The gamma voltage generator is connected with a plurality of channel circuits and is used for outputting the predetermined number of gamma voltages, and each channel circuit selects at least one gamma voltage according to input display data to generate a corresponding data voltage. The gamma voltage generator includes a plurality of basic buffers and a plurality of dynamic buffers. Each dynamic buffer is configured to operate in a first mode of not outputting a buffer voltage or in a second mode of outputting a buffer voltage, wherein, the plurality of dynamic buffers switch from the first mode to the second mode based on update or change of the display data. The buffer voltages from the two types of buffers are used to generate the gamma voltages.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: February 27, 2024
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventor: Chi-Yi Lo
  • Publication number: 20240028061
    Abstract: A feedback control system includes a driver chip and a power chip. The driver chip includes a first output terminal and a first input terminal. The first output terminal is to output a first detection voltage. The power chip includes a second input terminal and a second output terminal. The second input terminal is directly connected to the first output terminal, and the second output terminal is coupled to the first input terminal. The power chip generates a driving voltage according to the first detection voltage and outputs the driving voltage to the first input terminal.
    Type: Application
    Filed: June 14, 2023
    Publication date: January 25, 2024
    Inventors: Shan-Chiang TSOU, Chi-Yi LO, Jen-Hao LIAO
  • Publication number: 20230343121
    Abstract: Techniques of facilitating processing of at least one DICOM SC image—e.g., using a PC or workstation in a hospital or an institution—to automatically extract clinical data therein are provided. Characters associated with the clinical data are extracted from the at least one DICOM SC image based on configuration information associated with the at least one DICOM SC image, which configuration information is obtained based on the at least one DICOM SC image.
    Type: Application
    Filed: April 11, 2023
    Publication date: October 26, 2023
    Inventors: Poikavila Ullaskrishnan, Ren-Yi Lo
  • Publication number: 20230316983
    Abstract: A gamma voltage generator, a source driver and a display apparatus are provided. The gamma voltage generator is connected with a plurality of channel circuits and is used for outputting the predetermined number of gamma voltages, and each channel circuit selects at least one gamma voltage according to input display data to generate a corresponding data voltage. The gamma voltage generator includes a plurality of basic buffers and a plurality of dynamic buffers. Each dynamic buffer is configured to operate in a first mode of not outputting a buffer voltage or in a second mode of outputting a buffer voltage, wherein, the plurality of dynamic buffers switch from the first mode to the second mode based on update or change of the display data. The buffer voltages from the two types of buffers are used to generate the gamma voltages.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 5, 2023
    Inventor: Chi-Yi Lo
  • Publication number: 20230316975
    Abstract: A gamma voltage generator, a source driver and a display apparatus are provided. The gamma voltage generator includes a gamma voltage generating circuit and a plurality of buffers. The gamma voltage generating circuit has a plurality of voltage input end nodes and a plurality of voltage output end nodes for outputting the predetermined number of gamma voltages based on input voltages from the plurality of voltage input end nodes. Each buffer has an input end receive a corresponding gamma reference voltage, and an output end coupled to a corresponding voltage input end node. The gamma voltage generating circuit includes multiple resistor units connected in series, and each resistor unit is configured to have a second resistance value when operating in the second mode less than a first resistance value when operating in the first mode.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 5, 2023
    Inventor: Chi-Yi Lo
  • Patent number: 11678295
    Abstract: A contact tracking method and a related server are provided. In the method, the positioning information of multiple user equipments (UEs) is obtained. The UEs transmit wireless signals. The positioning information is determined based on the wireless signal. The wireless signal indicates a network provider identifier, a signal strength, or geolocation. The travel routes of the UEs are determined. Each travel route records the positioning information of one UE over time. The travel routes are analyzed to determine a contact situation between a first UE and a second UE of the UEs based on a contact criteria.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: June 13, 2023
    Assignee: Groundhog Inc.
    Inventors: Geoffrey Paul Bloch Mamlet, Ta-Gang Chiou, Tzu-Yi Lo
  • Patent number: 11656181
    Abstract: An inspection apparatus for inspecting a light-emitting diode wafer is provided. The inspection apparatus includes a Z-axis translation stage, a sensing probe, a height measurement module, a carrier, an illumination light source, and a processing device. The sensing probe is integrated with the Z-axis translation stage. The Z-axis translation stage is adapted to drive the sensing probe to move in a Z axis. The sensing probe includes a photoelectric sensor, a beam splitter, and a photoelectric sensing structure. One of the photoelectric sensor of the sensing probe and the height measurement module is adapted to receive a light beam penetrating the beam splitter, and the other one of the photoelectric sensor of the sensing probe and the height measurement module is adapted to receive a light beam reflected by the beam splitter. The carrier is configured to carry the light-emitting diode wafer. The illumination light source is configured to emit an illumination beam to irradiate the light-emitting diode wafer.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 23, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Yan-Rung Lin, Chih-Hsiang Liu, Chung-Lun Kuo, Hsiang-Chun Wei, Yeou-Sung Lin, Chieh-Yi Lo
  • Publication number: 20230152086
    Abstract: A heterogeneous integration detecting method and a heterogeneous integration detecting apparatus are provided. The heterogeneous integration detecting method includes the following. Under the condition of maintaining the same relative distance between an interference objective lens and a sample, the relative posture of the interference objective lens and the sample is continuously adjusted according to the change of an image of the sample in the field of view of the interference objective lens until a first optical axis of the interference objective lens is determined to be substantially perpendicular to the surface of the sample according to the image. The interference objective lens is replaced with an imaging objective lens and the geometric profile of at least one via of the sample is detected. A second optical axis of the imaging objective lens after replacement overlaps with the first optical axis of the interference objective lens before replacement.
    Type: Application
    Filed: December 27, 2021
    Publication date: May 18, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Hsiang-Chun Wei, Chih-Hsiang Liu, Yi-Sha Ku, Chung-Lun Kuo, Chun-Wei Lo, Chieh-Yi Lo
  • Publication number: 20230043777
    Abstract: A pin fixing type hand tool structure includes a tool head body, a grip body and an abutting fixing block, and cut corners are formed between the tool head body, the grip body and the abutting fixing block and provided for alignment and positioning, so that the three can be stably engaged with one another by the cut corners. The structure is simple and the assembling is convenient, and the production and assembling costs are reduced to achieve high structural stability and assembly convenience.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Inventors: SHU-YI LO, YU-JIE CHEN
  • Patent number: 11496048
    Abstract: A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: November 8, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Ming-Wei Chou, Sheng-Jian Chen, Chia-Chang Hsu, Cheng-Yi Lo
  • Publication number: 20220277396
    Abstract: A mobile computing device configured to manage a digital wallet card within a mobile wallet on the device by communicating with a central server. The mobile computing device continually communicates with the central server that stores policy information for an account associated with the digital wallet card. If the central server detects an update to the digital wallet card then, based on such indication, the mobile computing device generates an alert such as a notification to be displayed on a user interface of the mobile computing device indicating the existence of the update. The mobile computing device displays concurrently the notification of an update and an embedded link that when selected triggers downloading the update and replacing the digital wallet card with an updated digital wallet card in the mobile wallet.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: SACHA-RENE PARISEAU, KELVIN CHUN-YI LO
  • Publication number: 20220126904
    Abstract: A child stroller with simple structure and large accommodating space is provided and includes a stroller frame, a seat frame, a soft component and an accommodating component. The seat frame is disposed on the stroller frame. The soft component at least partially covers the stroller frame and the seat frame. The accommodating component is connected to a side of the soft component. An accommodating pocket is formed between the accommodating component and the soft component and for accommodating an object. An opening is formed on a side of the accommodating pocket and for allowing the object to enter into or exit from the accommodating pocket.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 28, 2022
    Applicant: Bambino Prezioso Switzerland AG
    Inventor: Ling-Yi Lo
  • Publication number: 20220086140
    Abstract: A computer-implemented method may include: receiving, from a first electronic device during an unauthenticated session, a request for provisioning data, the request associated with identification data insufficient to begin an authenticated session; determining, based on the identification data, whether the request for the provisioning data is associated with an existing account; when the request for the provisioning data is determined to be associated with an existing account, obtaining the provisioning data based on a modifier not available if the request for the provisioning data is not determined to be associated with an existing account; and sending the provisioning data to the first electronic device.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Applicant: The Toronto-Dominion Bank
    Inventors: Kelvin Chun-Yi LO, Guillaume ROBERGE, Francis CARLE, Robert BIGRAS, Brigitte HOUDE
  • Patent number: 11226605
    Abstract: A control layer automation device comprises a processor, one or more control layer applications, a database, a wireless interface, a device memory. Each control layer application is configured to perform a discrete set of automation functions. The database comprises a plurality of operator device identifiers and the wireless interface allows the one or more control layer applications to communicate with a plurality of operator devices via the plurality of operator device identifiers. The device memory comprises the one or more control layer applications. The control layer application manager is configured to manage execution of the one or more control layer applications on the processor.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: January 18, 2022
    Assignee: Siemens Aktiengesellschaft
    Inventors: George Lo, Livio Dalloro, Thomas Gruenewald, Christian Winkler, Peter Kob, Andreas Scholz, Mina Azib, Hermann Friedrich, Ren-Yi Lo