Patents by Inventor Yi-Lung Cheng
Yi-Lung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11972957Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.Type: GrantFiled: July 31, 2020Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-chun Yang, Chih-Lung Cheng, Yi-Ming Lin, Po-Chih Huang, Yu-Hsiang Juan, Xuan-Yang Zheng
-
Patent number: 7646207Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.Type: GrantFiled: September 4, 2007Date of Patent: January 12, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong Lin, Chin Chuan Peng, Shou-Chung Lee, Chien-Jung Wang, Chien Shih Tsai, Bi-Ling Lin, Yi-Lung Cheng
-
Patent number: 7512924Abstract: A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.Type: GrantFiled: January 17, 2006Date of Patent: March 31, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei Chen, Hsueh-Chung Chen, Yi-Lung Cheng, Shin-Puu Jeng
-
Publication number: 20090058434Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.Type: ApplicationFiled: September 4, 2007Publication date: March 5, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong Lin, Chin Chuan Peng, Shou-Chung Lee, Chien-Jung Wang, Chien Shih Tsai, Bi-Ling Lin, Yi-Lung Cheng
-
Patent number: 7470584Abstract: A TEOS deposition method. A mixture of gases is introduced into a process chamber, in which the mixture of gases comprises tetra-ethyl-ortho-silicate (TEOS) and N2. Compressive stress of a TEOS oxide film is increased by activating the mixture of gases.Type: GrantFiled: January 21, 2005Date of Patent: December 30, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lung Cheng, Hong-Jui Chang, Ying-Lang Wang
-
Patent number: 7449911Abstract: A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.Type: GrantFiled: March 29, 2007Date of Patent: November 11, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lung Cheng, Bi-Ling Liu, Chin-Chuang Peng, Chien-Shih Tsai, Hway-Chi Lin
-
Patent number: 7420277Abstract: The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.Type: GrantFiled: March 16, 2004Date of Patent: September 2, 2008Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Hsien-Wei Chen, Jiun-Lin Yeh, Shin-Puu Jeng, Yi-Lung Cheng
-
Publication number: 20080184805Abstract: A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.Type: ApplicationFiled: March 29, 2007Publication date: August 7, 2008Inventors: Yi-Lung Cheng, BL Lin, CC Peng, C.S. Tsai, Hway-Chi Lin
-
Publication number: 20070267737Abstract: Packaged devices and methods of forming packaged devices are provided. At least one device is disposed on a substrate. The material layer encapsulates the device and covers at least a portion of the substrate, wherein the material layer comprises at least a first portion adjacent to the device and a second portion over the first portion. The second portion has a thermal conductivity higher than a thermal conductivity of the first portion.Type: ApplicationFiled: May 17, 2006Publication date: November 22, 2007Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei Chen, Hsueh-Chung Chen, Yi-Lung Cheng
-
Patent number: 7296532Abstract: A method and reactant gas bypass system for carrying out a plasma enhanced chemical vapor deposition (PECVD) process with improved gas flow stability to avoid unionized reactant precursors and thickness non-uniformities the method including providing a semiconductor process wafer having a process surface within a plasma reactor chamber for carrying out at least one plasma process; supplying at least one reactant gas flow at a selected flow rate to bypass the plasma reactor chamber for a period of time to achieve a pre-determined flow rate stability; and, redirecting the at least one reactant gas flow into the plasma reactor chamber to carry out the at least one plasma process.Type: GrantFiled: December 18, 2002Date of Patent: November 20, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lung Cheng, Mo-Chen Liao, Eric Tsai, Sze-Au Wu, Ying-Lung Wang
-
Patent number: 7253121Abstract: A method for forming IMD films. A substrate is provided. A plurality of dielectric films are formed on the substrate, wherein each of the dielectric layers are deposited in-situ in one chamber with only one thermal cycle.Type: GrantFiled: September 9, 2004Date of Patent: August 7, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lung Cheng, Miao-Cheng Liao, Ying-Lang Wang
-
Publication number: 20070166887Abstract: A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.Type: ApplicationFiled: January 17, 2006Publication date: July 19, 2007Inventors: Hsien-Wei Chen, Hsueh-Chung Chen, Yi-Lung Cheng, Shin-Puu Jeng
-
Publication number: 20070158835Abstract: A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.Type: ApplicationFiled: January 12, 2006Publication date: July 12, 2007Inventors: Jian-Hong Lin, Hsueh-Chung Chen, Yi-Lung Cheng, Ta-Wei Lee, Chih-Tao Lin, Jyh-Kang Ting, Lee-Chung Lu
-
Patent number: 7208415Abstract: A plasma treatment method which is capable of extending the MTF (mean-time-to-failure) of metal interconnects fabricated on a semiconductor wafer substrate, is disclosed. The invention includes providing a trench typically in a dielectric layer on a substrate; depositing a metal in the trench; and exposing the metal to a nitrogen-based plasma. The plasma-treatment step accelerates grain growth and re-orients the grains in the metal to a closely-packed crystal orientation texture which approaches or approximates the <111> crystal orientation texture of copper.Type: GrantFiled: June 30, 2004Date of Patent: April 24, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jane-Bai Lai, Yi-Lung Cheng
-
Patent number: 7176571Abstract: A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.Type: GrantFiled: January 8, 2004Date of Patent: February 13, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yi-Lung Cheng, Ying-Lung Wang
-
Patent number: 7157367Abstract: A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).Type: GrantFiled: June 4, 2004Date of Patent: January 2, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hway Chi Lin, Yi-Lung Cheng, Chao-Hsiung Wang
-
Patent number: 7125802Abstract: Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.Type: GrantFiled: October 29, 2003Date of Patent: October 24, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Lang Wang, Shih-Chi Lin, Yi-Lung Cheng, Chi-Wen Liu, Ming-Hua Yoo, Wen-Kung Cheng, Jiann-Kwang Wang
-
Publication number: 20060166514Abstract: A TEOS deposition method. A mixture of gases is introduced into a process chamber, in which the mixture of gases comprises tetra-ethyl-ortho-silicate (TEOS) and N2. Compressive stress of a TEOS oxide film is increased by activating the mixture of gases.Type: ApplicationFiled: January 21, 2005Publication date: July 27, 2006Inventors: Yi-Lung Cheng, Hong-Jui Chang, Ying-Lang Wang
-
Publication number: 20060166458Abstract: A shallow trench isolation (STI) structure for semiconductor devices is formed using a deposited silicon layer formed over a polish stop layer formed over an oxide formed on a substrate. The polish stop layer may be nitride. An opening is formed extending through the deposited silicon layer and the nitride and oxide layers and extending into the substrate. A deposited oxide is formed filling the opening and extending over the top surface of deposited silicon layer. A chemical mechanical polishing operation polishes the deposited silicon layer at a rate faster than the deposited oxide layer to produce an STI with a convex portion extending above the nitride layer. Dishing problems are avoided and the structure may be subsequently planarized.Type: ApplicationFiled: January 26, 2005Publication date: July 27, 2006Inventors: Yi-Lung Cheng, Szu-An Wu, Yi-Lang Wang
-
Patent number: 7078336Abstract: A method is disclosed for reducing metal diffusion in a semiconductor device. After forming a first metal portion over a substrate, a silicon carbon nitro-oxide (SiCNO) layer is deposited on the first metal portion. A dielectric layer is deposited over the SiCNO layer, and an opening is generated in the SiCNO layer and the dielectric layer for a second metal portion to be connected to the first metal portion, wherein the SiCNO layer reduces the diffusion of the first metal portion into the dielectric layer.Type: GrantFiled: November 19, 2003Date of Patent: July 18, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lung Cheng, Ying-Lang Wang