Patents by Inventor Yi-Lung Cheng

Yi-Lung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6759347
    Abstract: A method of reducing plasma induced damage in semiconductor devices and fluorine damage to a metal containing layer including providing a semiconductor wafer including semiconductor devices including a gate oxide and a process surface including metal lines; carrying out a first high density plasma chemical vapor deposition (HDP-CVD) process to controllably produce a silicon rich oxide (SRO) layer including a relatively increased thickness at a center portion of the process surface compared to a peripheral portion of the process surface; and, carrying out a second HDP-CVD process in-situ to deposit a fluorine doped silicon dioxide layer over the SRO layer to fill a space between the metal lines.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: July 6, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Lung Cheng, Ming-Hwa Yoo, Sze-An Wu, Ying Lung Wang
  • Publication number: 20040118342
    Abstract: A method and reactant gas bypass system for carrying out a plasma enhanced chemical vapor deposition (PECVD) process with improved gas flow stability to avoid unionized reactant precursors and thickness non-uniformities the method including providing a semiconductor process wafer having a process surface within a plasma reactor chamber for carrying out at least one plasma process; supplying at least one reactant gas flow at a selected flow rate to bypass the plasma reactor chamber for a period of time to achieve a pre-determined flow rate stability; and, redirecting the at least one reactant gas flow into the plasma reactor chamber to carry out the at least one plasma process.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Lung Cheng, Mo-Chen Liao, Eric Tsai, Szu-An Wu, Ying-Lung Wang
  • Publication number: 20040097083
    Abstract: Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.
    Type: Application
    Filed: November 12, 2003
    Publication date: May 20, 2004
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Ying-Lang Wang, Shih-Chi Lin, Yi-Lung Cheng, Chi-Wen Liu, Ming-Hua Yoo, Wen-Kung Cheng, Jiann-Kwang Wang
  • Publication number: 20040084415
    Abstract: Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 6, 2004
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Ying-Lang Wang, Shih-Chi Lin, Yi-Lung Cheng, Chi-Wen Liu, Ming-Hua Yoo, Wen-Kung Cheng, Jiann-Kwang Wang
  • Patent number: 6713407
    Abstract: A method of depositing a plasma enhanced CVD metal nitride layer over an exposed copper surface in a semiconductor wafer manufacturing process to improve the metal nitride layer adhesion and to reduce copper hillock formation including providing a process surface which is an exposed copper surface; preheating the process surface; plasma sputtering the exposed copper surface in-situ to remove copper oxides; and, depositing a metal nitride layer in-situ according to a plasma enhanced CVD process at a selected deposition pressure to reduce plasma ion bombardment energy transfer and to suppress-copper hillock formation.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: March 30, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Lung Cheng, Wen-Kung Cheng, Sez-An Wu, Yi-Lung Wang, Shin-Chi Lin
  • Patent number: 6703317
    Abstract: A method of reducing an electrical charge imbalance on a wafer process surface including providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: March 9, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Lung Cheng, Ming-Hwa Yoo, Sze-An Wu, Ying-Lung Wang
  • Patent number: 6660638
    Abstract: Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: December 9, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ying-Lang Wang, Shih-Chi Lin, Yi-Lung Cheng, Chi-Wen Liu, Ming-Hua Yoo, Wen-Kung Cheng, Jiann-Kwang Wang
  • Publication number: 20030178141
    Abstract: A semiconductor processing apparatus and method are disclosed herein, including a plurality of process chambers, wherein at least one semiconductor processing operation occurs within each process chamber among the plurality of process chambers. Additionally, the apparatus and method disclosed herein include a robot mechanism for rotating each process chamber among the plurality of process chambers upon completion of an associated semiconductor processing operation. Such a robot mechanism may comprise a plurality of robots. Specifically, such a plurality of robots may include six robots configured on an associated carousel.
    Type: Application
    Filed: March 21, 2002
    Publication date: September 25, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Lung Cheng, Hui-Chi Lin, Szu-An Wu, Ying-Lang Wang
  • Patent number: 6602560
    Abstract: A method of removing residual fluorine present in a HDP-CVD chamber which includes a high pressure seasoning process, a dry-cleaning process, and a low-pressure deposition process.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 5, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Lung Cheng, Wen-Kung Cheng, Ming-Hwa Yoo, Szu-An Wu, Ying-Long Wang, Pei-Fen Chou
  • Patent number: 6584987
    Abstract: A method for cleaning residual material from a chemical vapor deposition (CVD) apparatus in situ employing dry etching. There is first employed a high density plasma chemical vapor deposition (HDP-CVD) method to deposit layers of silicon oxide material upon substrates within a chemical vapor deposition reactor apparatus. After removal of substrates, the reactor chamber is closed off. The interior of the reactor is then filled with a gas and a plasma formed therewithin, to which oxygen is added and the reactor allowed to come to an increased temperature and bake for a period of time. The reactor power is then turned off and the reactor evacuated. There is then carried out a normal cleaning step within the reactor chamber employing a reactive gas such as NF3, with greater cleaning efficiency due to the increased temperature caused by the baking step.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: July 1, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yi-Lung Cheng, Chun-Ching Tsan, Wen-Kung Cheng, Yin-Lang Wang
  • Publication number: 20030068448
    Abstract: A method of removing residual fluorine present in a HDP-CVD chamber which may include a high pressure seasoning process, a dry cleaning process and a low pressure deposition process is disclosed.
    Type: Application
    Filed: July 16, 2002
    Publication date: April 10, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co; Ltd
    Inventors: Yi-Lung Cheng, Wen-Kung Cheng, Ming-Hwa Yoo, Szu-An Wu, Ying-Lang Wang, Pei-Fen Chou
  • Patent number: 6479098
    Abstract: A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: November 12, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ming-Hwa Yoo, Yi-Lung Cheng, Szu-An Wu, Ying-Lang Wang