Patents by Inventor Yi-Min Lin
Yi-Min Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12231764Abstract: An image capturing method has: providing an image capturing area on a display screen of a user device; providing an indication area in the image capturing area; marking a license plate after identifying the license plate based on at least one license plate feature in the image capturing area; determining whether the marked license plate is located in the indication area and presented in a predetermined ratio; and capturing an image including the license plate in the image capturing area after the marked license plate is located in the indication area and presented in a predetermined ratio.Type: GrantFiled: July 28, 2022Date of Patent: February 18, 2025Assignee: GOGORO INC.Inventors: Yi-Chia Lin, Chih-Min Fu, I-Fen Shih
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Publication number: 20250056684Abstract: A heating device includes a resonant circuit, a detection unit and a control unit. The resonant circuit includes an inverter circuit and a resonant tank. The inverter circuit provides a resonant tank current and a resonant tank voltage. The resonant tank includes a heating coil, a resonant tank capacitor, a resonant tank equivalent inductor and a resonant tank equivalent resistor. The detection unit calculates an inductance of the resonant tank equivalent inductor according to a capacitance of the resonant tank capacitor, a resonant period and a first expression. The detection unit calculates a resistance of the resonant tank equivalent resistor according to the inductance of the resonant tank equivalent inductor, a time change value, a reference voltage value, a negative peak voltage value and a second expression.Type: ApplicationFiled: December 27, 2023Publication date: February 13, 2025Inventors: Ming-Shi Huang, Zheng-Feng Li, Jhih-Cheng Hu, Yi-Min Chen, Chun-Wei Lin
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Patent number: 12218082Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: GrantFiled: November 9, 2023Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240283467Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: ApplicationFiled: April 22, 2024Publication date: August 22, 2024Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chenrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
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Patent number: 11996865Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: GrantFiled: March 16, 2023Date of Patent: May 28, 2024Assignee: SK hynix Inc.Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
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Publication number: 20240143231Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Ning Chen, Jiangli Zhu, Yi-Min Lin, Fangfang Zhu
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Publication number: 20240070946Abstract: A computer device is provided, which includes a display device and a host. The host includes a keyboard, a camera, a storage device, and a processor. The storage device is configured to store an augmented-reality keyboard program. The processor is configured to execute the augmented-reality keyboard program to perform the following steps: detecting input method information of an operating system running on the host, and obtaining key arrangement of the keyboard; utilizing the camera to capture an operation image of the keyboard; and when a user's hand is recognized in the operation image, displaying a virtual keyboard on the display device according to the key arrangement and the input method information, and displaying a typing operation of the user's hand by superimposing an augmented-reality hand object on a key position of the virtual keyboard corresponding the typing operation of the user's hand.Type: ApplicationFiled: November 7, 2022Publication date: February 29, 2024Inventor: Yi-Min LIN
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Patent number: 11880600Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.Type: GrantFiled: September 2, 2021Date of Patent: January 23, 2024Assignee: Micron Technology, Inc.Inventors: Ning Chen, Jiangli Zhu, Yi-Min Lin, Fangfang Zhu
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Publication number: 20230410878Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.Type: ApplicationFiled: September 5, 2023Publication date: December 21, 2023Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
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Patent number: 11798614Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.Type: GrantFiled: August 31, 2021Date of Patent: October 24, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
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Patent number: 11747994Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.Type: GrantFiled: August 31, 2021Date of Patent: September 5, 2023Assignee: Micron Technology, Inc.Inventors: Chih-Kuo Kao, Yi-Min Lin
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Publication number: 20230231579Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: ApplicationFiled: March 16, 2023Publication date: July 20, 2023Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chenrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
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Patent number: 11611359Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: GrantFiled: August 7, 2020Date of Patent: March 21, 2023Assignee: SK hynix Inc.Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
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Publication number: 20230073518Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.Type: ApplicationFiled: August 31, 2021Publication date: March 9, 2023Inventors: Chih-Kuo Kao, Yi-Min Lin
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Publication number: 20230069439Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
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Publication number: 20230067281Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.Type: ApplicationFiled: September 2, 2021Publication date: March 2, 2023Inventors: Ning Chen, Jiangli Zhu, Yi-Min Lin, Fangfang Zhu
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Patent number: 11515897Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: GrantFiled: August 7, 2020Date of Patent: November 29, 2022Assignee: SK hynix Inc.Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
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Patent number: 11177835Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: GrantFiled: August 23, 2019Date of Patent: November 16, 2021Assignee: SK hynix Inc.Inventors: Kyoung Lae Cho, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
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Publication number: 20200373944Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: ApplicationFiled: August 7, 2020Publication date: November 26, 2020Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chengrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
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Publication number: 20200373943Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: ApplicationFiled: August 7, 2020Publication date: November 26, 2020Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chengrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR