Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.

Abstract: A computer device is provided, which includes a display device and a host. The host includes a keyboard, a camera, a storage device, and a processor. The storage device is configured to store an augmented-reality keyboard program. The processor is configured to execute the augmented-reality keyboard program to perform the following steps: detecting input method information of an operating system running on the host, and obtaining key arrangement of the keyboard; utilizing the camera to capture an operation image of the keyboard; and when a user's hand is recognized in the operation image, displaying a virtual keyboard on the display device according to the key arrangement and the input method information, and displaying a typing operation of the user's hand by superimposing an augmented-reality hand object on a key position of the virtual keyboard corresponding the typing operation of the user's hand.

Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.

Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.

Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.

Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.

Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.

Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A direct action solenoid valve includes: a valve body, on the valve body is disposed a water inlet port and two water outlet ports, the two water outlet ports are a first water outlet port and a second water outlet port respectively; a first water passage channel, formed between the water inlet port and the first water outlet port, and a second water passage channel, formed between the water inlet port and the second water outlet port; a chamber, formed between the first water passage channel and the second water passage channel; a control piece, disposed in the chamber, to control the first water outlet port to open; a solenoid valve head, disposed in the valve body; and a hydroelectric generator, disposed in the valve body to supply power to the solenoid valve head.

Abstract: A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. The encoded data includes a plurality of data blocks and each data block is included in two or more data codewords. Further, data codewords belonging to a same pair of data codewords share a common data block. The decoding apparatus is configured to iteratively decode data codewords using hard decoding and soft decoding, and to correct stuck errors by identifying failed data blocks based on shared blocks between failed data codewords.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.