Patents by Inventor Yi-Min Lin

Yi-Min Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149079
    Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a time elapsed since a last write operation with respect to a management unit comprising the one or more codewords; and applies the first read voltage to a set of memory cells storing the one or more codewords.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
  • Patent number: 12243577
    Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.
    Type: Grant
    Filed: September 5, 2023
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
  • Patent number: 12242313
    Abstract: A system determines a current state of an information handling system, and receives a sensor output signal. The system determines whether a status change of the sensor output signal relates to an expected state based on the current state and a previous state of the information handling system, and determines whether the sensor output signal is triggered by an external magnet. If the status change of the sensor output signal relates to the expected state and the sensor output signal is not triggered by the external magnet, then the system transitions the information handling system from the current state to the expected state.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: March 4, 2025
    Assignee: Dell Products L.P.
    Inventors: Chen Hsin Chang, Wan Shih Chien, Yi Min Lin
  • Publication number: 20240283467
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 22, 2024
    Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chenrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
  • Patent number: 11996865
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: May 28, 2024
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Publication number: 20240143231
    Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Ning Chen, Jiangli Zhu, Yi-Min Lin, Fangfang Zhu
  • Publication number: 20240070946
    Abstract: A computer device is provided, which includes a display device and a host. The host includes a keyboard, a camera, a storage device, and a processor. The storage device is configured to store an augmented-reality keyboard program. The processor is configured to execute the augmented-reality keyboard program to perform the following steps: detecting input method information of an operating system running on the host, and obtaining key arrangement of the keyboard; utilizing the camera to capture an operation image of the keyboard; and when a user's hand is recognized in the operation image, displaying a virtual keyboard on the display device according to the key arrangement and the input method information, and displaying a typing operation of the user's hand by superimposing an augmented-reality hand object on a key position of the virtual keyboard corresponding the typing operation of the user's hand.
    Type: Application
    Filed: November 7, 2022
    Publication date: February 29, 2024
    Inventor: Yi-Min LIN
  • Patent number: 11880600
    Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: January 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Ning Chen, Jiangli Zhu, Yi-Min Lin, Fangfang Zhu
  • Publication number: 20230410878
    Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
  • Patent number: 11798614
    Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 24, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
  • Patent number: 11747994
    Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Chih-Kuo Kao, Yi-Min Lin
  • Publication number: 20230231579
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Application
    Filed: March 16, 2023
    Publication date: July 20, 2023
    Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chenrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
  • Patent number: 11611359
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 21, 2023
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Publication number: 20230073518
    Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 9, 2023
    Inventors: Chih-Kuo Kao, Yi-Min Lin
  • Publication number: 20230069439
    Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
  • Publication number: 20230067281
    Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Inventors: Ning Chen, Jiangli Zhu, Yi-Min Lin, Fangfang Zhu
  • Patent number: 11515897
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Patent number: 11177835
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Publication number: 20200373944
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 26, 2020
    Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chengrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
  • Publication number: 20200373943
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 26, 2020
    Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chengrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR