Abstract: Memory systems and operating methods thereof comprise a memory storage and an error control coding (ECC) unit. The memory storage stores data which is split into a plurality of data chunks. The error control coding (ECC) unit is suitable for arranging each data chunk into codewords, each data chunk is arranged as part of at least two codewords, and mapping the codewords by reverse indexing the data chunks.

Abstract: An electrical dispensing assembly for a shower sprinkler having a body provided with multiple first outlets includes a dispensing disk having multiple second outlets communicating with the first outlets of the body, a rotation disk rotatably mounted on top of the dispensing disk and having at least two third outlets each alternately communicating with one of the second outlets so as to change water output pattern from the body and a driving device mounted on a side of the rotation disk to drive the rotation disk for a predetermined period of time.

Abstract: Techniques are described for optimizing a parity-check matrix for a low density parity check (LDPC) encoder. In an example, a first parity-check matrix is accessed. Based on a set of rules, an independent set of check nodes and variable nodes is determined. The set of rules specifies that a check node associated with the first parity-check matrix belongs to the independent set when the check node is connected to only one variable node from the independent set. The set of rules further specifies that a variable node associated with the first parity-check matrix belongs to the independent set when the variable node is connected to only one check node from the independent set. A size of the independent set is based on the set of rules. A second parity-check matrix is generated by at least applying a permutation to the first parity-check matrix based on the independent set.

Abstract: Techniques are described for decoding a codeword, including, obtaining a first message comprising a plurality of information bits and a plurality of parity bits, wherein the message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors, performing an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message, determining if the decoding was successful. Upon determining that the TPC decoding was not successful, determining one or more error locations in the second message based on a third constituent code using a third decoder. The third decoder determines the one or more error locations in a predetermined number of clock cycles.

Abstract: Memory systems and operating methods thereof comprise a memory storage and an error control coding (ECC) unit. The memory storage stores data which is split into a plurality of data chunks. The error control coding (ECC) unit is suitable for arranging each data chunk into codewords, each data chunk is arranged as part of at least two codewords, and mapping the codewords by reverse indexing the data chunks.

Abstract: Systems for performing turbo product code decoding includes an error intersection identifier determining a set of one or more error intersections using a set of error-containing codewords, and updating, based at least in part on Chase decoding performed on the set of error-containing codewords, the set of error intersections to obtain an updated set of one or more error intersections, a bit location selector suitable for selecting, from the set of error intersections, a set of one or more least reliable bit locations using soft information associated with the set of error-containing codewords, and a Chase decoder performing Chase decoding on the set of error-containing codewords based on a first value being a number of least reliable bit locations and a second value being a maximum number of allowable flips allowed out of the number of least reliable bit locations.

Abstract: A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.

Abstract: An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode in accordance with the NAND data and generate decoder information by the decoder; predict a BER in accordance with at least the decode information by the BER predictor; and evaluate the predicted BER and generate evaluation result by the BER predictor.

Abstract: Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, a system accesses and decodes a generalized product code (GPC) codeword by using at least one of a plurality of Chase decoding procedures available on the system. A first Chase decoding procedure is configured according to first values for a set of decoding parameters. A second Chase decoding procedure is configured according to second values for the set of decoding parameters. The second values are different from the first values. The first Chase decoding procedure has a smaller latency and a higher bit error rate (BER) relative to the second Chase decoding procedure based on the first values and the second values for the set of decoding parameters.

Abstract: A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, each data block having a number of data bits. The decoding apparatus is configured to decode in parallel two or more codewords, which share a common data block, to determine error information associated with each codeword. For each error, the error information identifies a data block having the and associated error bit patterns. The decoding apparatus is configured to update the two or more codewords based on the identified data blocks having errors and the associated error bit patterns.

Abstract: A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.

Abstract: Techniques are described for codeword decoding. In an example, a system computes a checksum for a codeword based on the codeword and a parity check matrix. The system compares the checksum to thresholds. Each threshold is associated with a different decoder from a plurality of decoders available on the system. The system selects a decoder from the plurality of decoders. The decoder is selected based on the comparison of the checksum to the thresholds. The system decodes the codeword by using the selected decoder.

Abstract: Techniques are described for optimizing a parity-check matrix for a low density parity check (LDPC) encoder. In an example, a first parity-check matrix is accessed. Based on a set of rules, an independent set of check nodes and variable nodes is determined. The set of rules specifies that a check node associated with the first parity-check matrix belongs to the independent set when the check node is connected to only one variable node from the independent set. The set of rules further specifies that a variable node associated with the first parity-check matrix belongs to the independent set when the variable node is connected to only one check node from the independent set. A size of the independent set is based on the set of rules. A second parity-check matrix is generated by at least applying a permutation to the first parity-check matrix based on the independent set.

Abstract: An apparatus for decoding a TPC codeword is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to receive a first set of soft information corresponding to the TPC codeword. The TPC codeword includes at least one codeword corresponding to each of first, second, and third dimensions. The processor is further configured to iteratively perform a first soft decoding procedure on the at least one codeword corresponding to the first dimension to generate a first candidate codeword and upon determining that the first candidate codeword is not a correct codeword, and perform a second decoding procedure on the at least one codeword corresponding to the third dimension to generate a second candidate codeword. The second decoding procedure generates a second set of soft information to be used at a later iteration of the first decoding procedure.

Abstract: Techniques are described for decoding a first message. In one example, the techniques include obtaining a second message comprising reliability information corresponding to each bit in the first message, performing a soft decision decoding procedure on the second message to generate a decoded codeword, wherein the soft decision decoding procedure comprises a joint decoding and miscorrection avoidance procedure, and outputting the decoded codeword.

Abstract: A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. The encoded data includes a plurality of data blocks and each data block is included in two or more data codewords. Further, data codewords belonging to a same pair of data codewords share a common data block. The decoding apparatus is configured to iteratively decode data codewords using hard decoding and soft decoding, and to correct stuck errors by identifying failed data blocks based on shared blocks between failed data codewords.

Abstract: In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.

Abstract: Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords.

Abstract: An apparatus for decoding is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to obtain a first codeword comprising one or more information bits and one or more parity bits, obtain a first parameter corresponding to a code rate of the first codeword, and decode the first codeword using a multi-rate decoder to generate a decoded codeword. The multi rate decoder performs a code reconstruction procedure on the first codeword to generate a reconstructed codeword, and decodes the reconstructed codeword. The processor is further configured to output the decoded codeword.

Abstract: A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. In coarse decoding, the decoder decodes in parallel two or more codewords, which share a common block of bits, to determine error information. Next, the decoder corrects errors in a first codeword based on the error information. Then, it is determined if the shared common block of data bits is corrected. If the shared common data block is updated, then error correction based on the error information is prohibited in codewords sharing the common block of data bits with the first codeword. In fine decoding, a single codeword is decoded at a time for error correction.