Abstract: Techniques are described for protecting miscorrection in a codeword. In one example, the techniques include obtaining a first set of data to be encoded using a product code comprising one or more constituent codes, and generating a second set of data by performing a miscorrection avoidance procedure on the first set of data. The miscorrection avoidance procedure decreases a probability of miscorrection at a decoder. The techniques further includes jointly encoding the first and the second set of data using an encoding procedure corresponding to the product code to generate at least one encoded codeword, and storing the encoded codeword in the memory.

Abstract: Techniques are described for decoding a message. In one example, the techniques include obtaining a first message comprising a plurality of information bits and a plurality of parity bits, decoding the first message using an iterative decoding algorithm to generate a first bit sequence, generating a miscorrection metric based at least on the first bit sequence and one or more reliability values corresponding to one or more bits in the first message, determining whether a miscorrection happened in the decoder by comparing the miscorrection metric with a first threshold, and upon determining that a miscorrection did not happen, outputting the first bit sequence as a decoded message.

Abstract: Techniques are described for decoding a codeword, including, obtaining a first message comprising a plurality of information bits and a plurality of parity bits, wherein the message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors, performing an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message, determining if the decoding was successful. Upon determining that the TPC decoding was not successful, determining one or more error locations in the second message based on a third constituent code using a third decoder. The third decoder determines the one or more error locations in a predetermined number of clock cycles.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.

Abstract: Systems for performing turbo product code decoding may include an error intersection identifier suitable for determining a set of one or more error intersections using a set of error-containing codewords, and updating, based at least in part on Chase decoding performed on the set of error-containing codewords, the set of error intersections to obtain an updated set of one or more error intersections, a bit location selector suitable for selecting, from the set of error intersections, a set of one or more least reliable bit locations using soft information associated with the set of error-containing codewords, and a Chase decoder suitable for performing Chase decoding on the set of error-containing codewords based on a first value being a number of least reliable bit locations and a second value being a maximum number of allowable flips allowed out of the number of least reliable bit locations.

Abstract: Systems may include a memory storage suitable for storing data, an encoder suitable for encoding data into codewords arranged in an array of a number of rows and a number of columns, and a decoder suitable for receiving the encoded codewords, decoding the encoded codewords, and detecting miscorrections in the decoding.

Abstract: A hinge path is used to determine if a first possible root is a root of an error location polynomial. A positive limb path is used to determine if a second possible root is a root of the error location polynomial, including by using a sequence of coefficients associated with the error location polynomial. The sequence of coefficients is reversed and a negative limb path is used to determine if a third possible root is a root of the error location polynomial, including by using the reversed sequence of coefficients, wherein the negative limb path is a copy of the positive limb path.

Abstract: A method for decoding low-density parity check (LDPC) codes, includes computing an initial syndrome of an initial output, obtaining an initial number of unsatisfied checks based on the computed initial syndrome, and when the initial number of unsatisfied checks is greater than zero, computing a reliability value with a parity check, performing a bit flip operation, computing a subsequent syndrome of a subsequent output, and ending decoding when a number of unsatisfied checks obtained based on the computed subsequent syndrome is equal to zero.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A power adapter between an alternating current (AC) source and an external direct current (DC) consumer device consumes no electrical power until the DC device is connected to the power adapter. The power adapter includes a first magnet, a second magnet which is repelled by the first magnet, and a movable conductive member arranged on the second magnet. The insertion of the external DC device pushes the second magnet towards the first magnet and establishes a connection between the AC power source and the power adaptor. When the external device is removed, the movable conductive member is driven away by a repulsive force between the magnets to disconnect the external AC power source from the power adapter.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.

Abstract: In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to the ELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.

Abstract: A power adapter between an alternating current (AC) source and an external direct current (DC) consumer device consumes no electrical power until the DC device is connected to the power adapter. The power adapter includes a first magnet, a second magnet which is repelled by the first magnet, and a movable conductive member arranged on the second magnet. The insertion of the external DC device pushes the second magnet towards the first magnet and establishes a connection between the AC power source and the power adaptor. When the external device is removed, the movable conductive member is driven away by a repulsive force between the magnets to disconnect the external AC power source from the power adapter.

Abstract: An apparatus of processing polynomials includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.

Abstract: A power device includes a power supply module, a first electrical isolation unit, a second electrical isolation unit, a feedback control unit, and a comparing unit. The power supply module includes a feedback compensating terminal and an output terminal, the feedback compensating terminal provides a related voltage of output power, and the output terminal provides an output voltage. When the related voltage of output power is smaller than the predetermined voltage, the comparing unit controls the first electrical isolation unit to change operation of the feedback control unit and the second electrical isolation unit, to allow the power supply module to adjust the output voltage.

Abstract: The present invention discloses an ultrasonic apparatus with an adjustable horn. The ultrasonic apparatus comprises a transmission device, a horn and an ultrasonic transceiver device. The horn and the transmission device are geared by a helical gear. The ultrasonic transceiver device is connected to the end of the helical gear. When the transmission device moves the horn to a first position, the ultrasonic transceiver device is applied for on/off control; while the transmission device moves the horn to a second position, the ultrasonic sensor is applied for digital control.