Patents by Inventor Yi-Ming Chen

Yi-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200373405
    Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a first gate spacer, and an epitaxy structure. The substrate has a semiconductor fin. The isolation structure is over the substrate and laterally surrounds the semiconductor fin. The first gate structure is over the substrate and crosses the semiconductor fin. The first gate spacer extends along a sidewall of the first gate structure, in which the first gate spacer has a stepped sidewall distal to the first gate structure. The epitaxy structure is over the semiconductor fin, in which the epitaxy structure is in contact with the stepped sidewall of the first gate spacer.
    Type: Application
    Filed: August 8, 2020
    Publication date: November 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lun CHEN, Bau-Ming WANG, Chun-Hsiung LIN
  • Patent number: 10845008
    Abstract: An LED filament comprises at least one LED section, a conductive section, two conductive electrodes and a light conversion layer. The conductive section is used to electrically connect two adjacent LED sections. The two conductive electrodes are electrically connected to each of the LED sections. Each of the LED sections includes at least two LED chips electrically connected to each other. The light conversion layer covers the LED sections, the conductive sections and the conductive electrodes, and a part of the two electrodes is exposed respectively. Since the LED filament includes the LED section and the conductive section, when the LED filament is bent, the stress is easily concentrated on the conductive section. Therefore, the breakage probability of the conductive wires connected within the LED section is reduced during bending. The quality of the LED filament and its application is improved.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 24, 2020
    Assignee: ZHEJIANG SUPER LIGHTING ELECTRIC APPLIANCE CO., LTD.
    Inventors: Tao Jiang, Wei-Hong Xu, Yukihiro Saito, Hayato Unagiike, Ai-Ming Xiong, Jun-Feng Xu, Yi-Ching Chen
  • Patent number: 10821487
    Abstract: A cleaning apparatus for concentration controller of coating machine may include a pulse bubble generator and a container used for cleaning a concentration controller of a coating machine and a tube thereof. The pulse bubble generator has a bubble-generating end connected to the container through a pipe, and the container is filled with a plentiful detergent. The pulse bubble generator is configured to pump air into the detergent with a pulse per time, and a large amount of detergent bubbles are adapted to be generated in the container. The detergent bubbles are configured to be pumped by the concentration controller into the tube and the concentration controller so as to complete cleaning effect of the tube and the concentration controller.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 3, 2020
    Inventors: Chi-Ming Chen, Yi-Nung Chung
  • Patent number: 10824936
    Abstract: A recycling system and a method based on deep-learning and computer vision technology are disclosed. The system includes a trash sorting device and a trash sorting algorithm. The trash sorting device includes a trash arraying mechanism, trash sensors, a trash transfer mechanism and a controller. The trash arraying mechanism is configured to process trash in a batch manner. The controller drives the trash arraying mechanism according to the signals of trash sensors and controls the sorting gates of the trash sorting mechanism to rotate. The trash sorting algorithm makes use of the images of trash, wherein the images are taken by cameras in different directions. The trash sorting algorithm includes a dynamic object detection algorithm, an image pre-processing algorithm, an identification module and a voting and selecting algorithm. The identification module is based on the convolutional neural networks (CNNs) and may at least identify four kinds of trash.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: November 3, 2020
    Assignee: National Chiao Tung University
    Inventors: Bing-Fei Wu, Wan-Ju Tseng, Yu-Ming Chen, Bing-Jhang Wu, Yi-Chiao Wu, Meng-Liang Chung
  • Patent number: 10804163
    Abstract: A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 10794545
    Abstract: An LED light bulb having a bulb base and a bulb shell connected with the bulb base, the bulb shell having a layer of luminescent material formed in the material of the bulb shell. A stem with a stand extending to the center of the bulb shell is disposed in the bulb shell. A flexible LED filament is disposed in the bulb shell, at least half of the LED filament is disposed around a center axle of the LED light bulb, where the center axle is coaxial with the axle of the stand and two conductive supports, each of which are connected with the stem and the LED filament. A driving circuit is electrically connected with the two conductive supports and the bulb base. Additionally, a plurality of supporting arms has two ends, with one end connected to the stem and the other end connected to the LED filament.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: October 6, 2020
    Assignee: ZHEJIANG SUPER LIGHTING ELECTRIC APPLIANCE CO., LT
    Inventors: Tao Jiang, Wei-Hong Xu, Yukihiro Saito, Hayato Unagiike, Al-Ming Xiong, Jun-Feng Xu, Yi-Ching Chen
  • Patent number: 10795388
    Abstract: A voltage adjustment device comprises a voltage detector and a signal emitter. The voltage detector electrically connects to an electrical device through a power rail and obtains a voltage detected value of the power rail. The signal emitter electrically connects to the voltage detector and is configured to electrically connect to a host and a power board. The signal emitter generates a power good signal and sends the power good signal to the host when the voltage detected value is larger than a baseline voltage value for the first time. After sending the power good signal, the signal emitter generates a voltage adjustment signal according to the voltage detected value and is configured to send the voltage adjustment signal to the power board for selectively adjusting a voltage provided by the power board.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 6, 2020
    Assignee: WIWYNN CORPORATION
    Inventors: Yi-Hao Chen, Chia-Ming Tsai
  • Patent number: 10763365
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Ching, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Publication number: 20200274022
    Abstract: A semiconductor light-emitting device comprises a substrate; a first adhesive layer on the substrate; multiple epitaxial units on the first adhesive layer; a second adhesive layer on the multiple epitaxial units; multiple first electrodes between the first adhesive layer and the multiple epitaxial units, and contacting the first adhesive layer and the multiple epitaxial units; and multiple second electrodes between the second adhesive layer and the multiple epitaxial units, and contacting the second adhesive layer and the multiple epitaxial units; wherein the multiple epitaxial units are totally separated.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Hsin-Chih Chiu, Chih-Chiang Lu, Chun-Yu Lin, Ching-Huai Ni, Yi-Ming Chen, Tzu-Chieh Hsu, Ching-Pei Lin
  • Patent number: 10752673
    Abstract: Disclosed herein are methods for high-throughput screening of a functional antibody fragment for an immunoconjugate that targets a protein antigen. The method combines a phage-displayed synthetic antibody library and high-throughput cytotoxicity screening of non-covalently assembled immunotoxins or cytotoxic drug to identify highly functional synthetic antibody fragments for delivering toxin payloads.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 25, 2020
    Assignee: ACADEMIA SINICA
    Inventors: An-Suei Yang, Hong-Sen Chen, Chung-Ming Yu, Shin-Chen Hou, Wei-Ying Kuo, Yi-Kai Chiu, Yueh-Liang Tsou, Hung-Ju Hsu, Hwei-Jiung Wang, Shih-Hsien Chuang, Chao-Pin Lee
  • Patent number: 10754400
    Abstract: A control method for data storage system includes obtaining a correlation coefficient corresponding to storage devices using a control device, and adjusting the link speed of one of the storage devices using the control device.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 25, 2020
    Assignee: WIWYNN CORPORATION
    Inventors: Cheng Kuang Hsieh, Kai Sheng Chen, Chia Ming Tsai, Yi-Hao Chen
  • Publication number: 20200266274
    Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
  • Patent number: 10741667
    Abstract: A method includes forming a semiconductor fin over a substrate; forming a helmet stack on a top surface of the semiconductor fin; forming a spacer layer over the helmet stack and on opposite sidewalls of the semiconductor fin; and etching the helmet layer and the spacer layer to expose the top surface and the sidewalls of the semiconductor fin.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lun Chen, Bau-Ming Wang, Chun-Hsiung Lin
  • Publication number: 20200251365
    Abstract: A method for fault detection in a fabrication facility is provided. The method includes moving a wafer carrier along a predetermined path multiple times using a transportation apparatus. The method also includes collecting data associated with an environmental condition within the wafer carrier or around the wafer carrier using a metrology tool on the predetermined path in a previous movement of the transportation apparatus. The method further includes measuring the environmental condition within the wafer carrier or around the wafer carrier using the metrology tool during the movement of the wafer carrier. In addition, the method includes issuing a warning when the measured environmental condition is outside a range of acceptable values. The range of acceptable values is derived from the data collected in the previous movement of the transportation apparatus.
    Type: Application
    Filed: April 24, 2020
    Publication date: August 6, 2020
    Inventors: Powen HUANG, Yao-Yuan SHANG, Kuo-Shu TSENG, Yen-Yu CHEN, Chun-Chih LIN, Yi-Ming DAI
  • Patent number: 10734551
    Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: August 4, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Patent number: 10732738
    Abstract: A system module of customizing a screen image based on a non-invasive data-extraction system, and a method thereof are disclosed. The system module is applicable to a machine controller controlling a machine, and sensors are disposed around the machine. In the system module, an image capture device receives an image of an original screen from the machine controller, and transmits the image to the non-invasive data-extraction system for extracting information, and a software control system integrates data measured by the sensors with the information, and combined the integration result with a customized screen image, and an extra control component is embedded in an original operation screen of the machine controller. The customized screen image is shown on the machine controller to display information by more visual manner. Furthermore, the signal receiving device and an HID simulation device can be used to provide a basic function of a KVM switch.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 4, 2020
    Assignee: Adlink Technology Inc.
    Inventors: Chua-Hong Ng, Chao-Tung Yang, Wei-Hung Chen, Tsan-Ming Yu, Shih-Hsun Lin, Yang-Chung Tseng, Chih-Fu Hsu, Chien-Hsun Tu, Te-Cheng Chiu, Yi-Wei Lin, Jen-Chi Hsu
  • Patent number: 10727113
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • Publication number: 20200225551
    Abstract: A reflective display device includes a thin-film transistor (TFT) array substrate, a front panel laminate (FPL), a front protection sheet, a back protection sheet, a light blocking layer, and a light source. The front panel laminate is located on the TFT array substrate, and has a transparent conductive layer and a display medium layer. The display medium layer is located between the transparent conductive layer and the TFT array substrate. The front protection sheet is located on the front panel laminate. The back protection sheet is located below the TFT array substrate. The light blocking layer at least covers a lateral surface of the back protection sheet. The light source faces toward a lateral surface of the front panel laminate, a lateral surface of the TFT array substrate, and the lateral surface of the back protection sheet.
    Type: Application
    Filed: July 24, 2019
    Publication date: July 16, 2020
    Inventors: Chia-Chi CHANG, Chih-Chun CHEN, Chi-Ming WU, Yi-Ching WANG, Jia-Hung CHEN, Cheng-Hsien LIN
  • Publication number: 20200212217
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 2, 2020
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Patent number: D894850
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 1, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chun-Fu Tsai, Yao-Ning Chan, Yi-Tang Lai, Yi-Ming Chen, Shih-Chang Lee