Patents by Inventor Yi-Ming Lin

Yi-Ming Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450787
    Abstract: An optoelectronic semiconductor device includes a semiconductor stack, an electrode, and a plurality of contact portions. The semiconductor stack includes a first type semiconductor structure, an active structure on the first type semiconductor structure, and a second type semiconductor structure on the active structure. The first type semiconductor structure includes a first protrusion part, a second protrusion part and a platform part between the first protrusion part and the second protrusion part. The semiconductor stack includes a thickness. The electrode on the second type semiconductor structure includes a region corresponding to the first protrusion. The contact portions are located at the second protrusion part without being at the first protrusion part. The contact portions are attached to the first type semiconductor structure.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: September 20, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Chung-Hao Wang, Yu-Chi Wang, Yi-Ming Chen, Yi-Yang Chiu, Chun-Yu Lin
  • Patent number: 11443961
    Abstract: An apparatus for fabricating a semiconductor device has a housing defining a buffer chamber, a plurality of reactor ports formed in the housing for establishing interfaces with a plurality of process chambers that are to receive a wafer during a fabrication process to fabricate the semiconductor device, a wafer positioning robot positioned within the buffer chamber to transport the wafer between the plurality of process chambers through the plurality of reactor ports, a purge port formed in the housing for introducing a purge gas into the buffer chamber, a pump port formed in the housing for exhausting a portion of the purge gas from the buffer chamber, and a first flow enhancer that directs the purge gas flowing in an axial direction along a longitudinal axis of the purge port into the buffer chamber in a plurality of radial directions relative to the longitudinal axis.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, ltd.
    Inventors: Chih-Tsung Lee, Sheng-Chun Yang, Yun-Tzu Chiu, Chao-Hung Wan, Yi-Ming Lin, Chyi-Tsong Ni
  • Publication number: 20220286265
    Abstract: Provided are a time-domain resource determination method and apparatus, and a terminal device. The method comprises: a terminal device determining a first slot set within a first period according to a first time division duplexing (TDD) configuration in radio resource control (RRC) signaling or a second TDD configuration in a physical sidelink broadcast channel (PSBCH); and the terminal device selecting some slots from the first slot set according to a first bitmap, wherein the slots constitute time-domain resources in a resource pool.
    Type: Application
    Filed: May 17, 2022
    Publication date: September 8, 2022
    Inventors: Zhenshan ZHAO, Yi DING, Huei-Ming LIN
  • Patent number: 11434277
    Abstract: Disclosed herein are methods for high-throughput screening of a virus-specific neutralizing antibody. According to certain embodiments of the present disclosure, the virus is an influenza virus. Also disclosed herein are the antibodies selected by the high-throughput screening method, and the uses thereof in the prophylaxis and/or treatment of viral infection.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: September 6, 2022
    Assignee: ACADEMIA SINICA
    Inventors: An-Suei Yang, Ing-Chien Chen, Yi-Kai Chiu, Chung-Ming Yu, Cheng-Chung Lee, Chao-Ping Tung, Yueh-Liang Tsou, Yi-Jen Huang, Chia-Lung Lin, Hong-Sen Chen, Hwei-Jiung Wang
  • Publication number: 20220279487
    Abstract: A resource exclusion method and apparatus, and a device and a storage medium, relating to the field of communications. The method is applied to a first terminal, and comprises: determining a quantity of reserved periods Q of a second terminal according to a resource reserved period Prx and a threshold Tscal, the threshold Tscal being determined according to a predetermined value; and when a first resource set overlaps a second resource set, excluding a target resource in the first resource set from a candidate resource set in a resource selection window, the second resource set being determined according to the resource reserved period Prx and the quantity of reserved periods Q, wherein the first resource set comprises at least one resource that may be used by the first terminal, and the second resource set comprises at least one resource that can be used by the second terminal.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Applicant: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Yi DING, Zhenshan ZHAO, Huei-Ming LIN
  • Publication number: 20220278242
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Application
    Filed: May 13, 2022
    Publication date: September 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han LIN, Chao-Ching CHANG, Yi-Ming LIN, Yen-Ting CHOU, Yen-Chang CHEN, Sheng-Chan LI, Cheng-Hsien CHOU
  • Publication number: 20220278128
    Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.
    Type: Application
    Filed: June 15, 2021
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Yi-Ching Liu, Sai-Hooi Yeong, Yih Wang, Yu-Ming Lin
  • Patent number: 11424359
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Publication number: 20220249209
    Abstract: An oral scanner including a heating element, a reflecting element and a temperature difference generating element is provided. The temperature difference generating element has a high temperature end and a low temperature end. The high temperature end is connected to the reflecting element to heat the reflecting element, and the low temperature end is connected to the heating element to cool the heating element.
    Type: Application
    Filed: January 24, 2022
    Publication date: August 11, 2022
    Applicant: Qisda Corporation
    Inventors: Chien-Hung LIN, Po-Fu WU, Jun-Ming SHEN, Szu-Fan CHEN, Yi-Ling LO
  • Patent number: 11411097
    Abstract: Provided is a semiconductor device including a substrate, a plurality of memory cells, and at least one dummy gate structure. The substrate has a memory cell region and a dummy region. The memory cells are disposed on the substrate in the memory cell region. Each memory cell includes: adjacent two stack structures disposed on the substrate; two select gates respectively disposed outside the adjacent two stack structures; and an erase gate disposed between the adjacent two stack structures. The erase gate has a step between a topmost top surface and a lowermost top surface of the erase gate. The at least one dummy gate structure is disposed on the substrate in the dummy region.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chuan Lin, Chiang-Ming Chuang, Shang-Yen Wu
  • Patent number: 11404091
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Chenchen Jacob Wang, Yi-Ching Liu, Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin, Yih Wang
  • Publication number: 20220240368
    Abstract: A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.
    Type: Application
    Filed: November 21, 2021
    Publication date: July 28, 2022
    Inventors: Pei-Wei WANG, Heng-Ming NIEN, Ching-Sheng CHEN, Yi-Pin LIN, Shih-Liang CHENG
  • Patent number: 11398424
    Abstract: A semiconductor package structure includes a substrate. The substrate includes a first ground layer. The first ground layer has a body and a first tooth protruding from a side of the body. The first tooth has a first lateral side. The first lateral side of the first tooth is inclined relative to the side of the body in a top view of the first ground layer.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: July 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jaw-Ming Ding, Ren-Hung Chou, Yi-Hung Lin
  • Publication number: 20220229494
    Abstract: Techniques for proving haptic feedback in computing systems are described. In operation, an input representing utilisation parameters of an electronic pen is received. In an example, the electronic pen may be electronically coupled to the computing system. Based on the received utilisation parameters, the computing system provides a pattern of haptic feedback to the user.
    Type: Application
    Filed: September 16, 2019
    Publication date: July 21, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Charles J. Stancil, Tai Hsiang Chen, Hung-Ming Chen, Simon Wong, Hsiang-Ta Ke, Yi-Hsien Lin, Jung-Hsing Wang
  • Publication number: 20220223727
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 14, 2022
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Patent number: 11387123
    Abstract: A method for fault detection in a fabrication facility is provided. The method includes moving a wafer carrier along a predetermined path multiple times using a transportation apparatus. The method also includes collecting data associated with an environmental condition within the wafer carrier or around the wafer carrier using a metrology tool on the predetermined path in a previous movement of the transportation apparatus. The method further includes measuring the environmental condition within the wafer carrier or around the wafer carrier using the metrology tool during the movement of the wafer carrier. In addition, the method includes issuing a warning when the measured environmental condition is outside a range of acceptable values. The range of acceptable values is derived from the data collected in the previous movement of the transportation apparatus.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Powen Huang, Yao-Yuan Shang, Kuo-Shu Tseng, Yen-Yu Chen, Chun-Chih Lin, Yi-Ming Dai
  • Patent number: 11374108
    Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a first gate spacer, and an epitaxy structure. The substrate has a semiconductor fin. The isolation structure is over the substrate and laterally surrounds the semiconductor fin. The first gate structure is over the substrate and crosses the semiconductor fin. The first gate spacer extends along a sidewall of the first gate structure, in which the first gate spacer has a stepped sidewall distal to the first gate structure. The epitaxy structure is over the semiconductor fin, in which the epitaxy structure is in contact with the stepped sidewall of the first gate spacer.
    Type: Grant
    Filed: August 8, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lun Chen, Bau-Ming Wang, Chun-Hsiung Lin
  • Patent number: 11335817
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han Lin, Chao-Ching Chang, Yi-Ming Lin, Yen-Ting Chou, Yen-Chang Chen, Sheng-Chan Li, Cheng-Hsien Chou
  • Publication number: 20220139980
    Abstract: An image sensor may include a polydimethylsiloxane (PDMS) layer that is subwavelength, hydrophobic, and/or antireflective. The PDMS layer may be fabricated to include a surface having a plurality of nanostructures (e.g., an array of convex protuberances and/or an array of concave recesses). The nanostructures may be formed through the use of a porous anodic aluminum oxide (AAO) template that uses a plurality of nanopores to form the array of convex protuberances and/or the array of concave recesses. The nanostructures may each have a respective width that is less than the wavelength of incident light that is to be collected by the image sensor to increase light absorption by increasing the angle of incidence for which the image sensor is capable of collecting incident light. This may increase the quantum efficiency of the image sensor and may increase the sensitivity of the image sensor.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Yi-Ming LIN, Chen-Chi WU, Chen-Kuei CHUNG
  • Publication number: 20220037169
    Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Inventors: Sheng-chun YANG, Chih-Lung CHENG, Yi-Ming LIN, Po-Chih HUANG, Yu-Hsiang JUAN, Xuan-Yang ZHENG