Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Abstract: Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: In some embodiments, the present disclosure relates to a method that includes depositing multiple hard mask layers over an interconnect dielectric layer. A first patterning layer is deposited over the multiple hard mask layers, and a first masking structure is formed over the first masking structure. The first masking structure has openings formed by a first extreme ultraviolet (EUV) lithography process. Portions of the first patterning layer are removed according to the first masking structure. A second masking structure is formed within the patterned first patterning layer. A third masking structure is formed over a topmost one of the hard mask layers and has openings formed by a second EUV lithography process. Removal processes are performed to pattern the multiple hard mask layers to form openings in the interconnect dielectric layer, and interconnect wires having rounded corners are formed within the openings of the interconnect dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes forming a source/drain region on a semiconductor fin. The source/drain region is adjacent to a dummy gate. The method further includes forming a first dielectric layer over the source/drain region and the dummy gate. The first dielectric layer has a dielectric constant of 3.5 or less. The first dielectric layer may include boron nitride or silicon dioxide with Si-CH3 bonds.

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Abstract: In some embodiments, the present disclosure relates to a method that includes depositing multiple hard mask layers over an interconnect dielectric layer. A first patterning layer is deposited over the multiple hard mask layers, and a first masking structure is formed over the first masking structure. The first masking structure has openings formed by a first extreme ultraviolet (EUV) lithography process. Portions of the first patterning layer are removed according to the first masking structure. A second masking structure is formed within the patterned first patterning layer. A third masking structure is formed over a topmost one of the hard mask layers and has openings formed by a second EUV lithography process. Removal processes are performed to pattern the multiple hard mask layers to form openings in the interconnect dielectric layer, and interconnect wires having rounded corners are formed within the openings of the interconnect dielectric layer.

Abstract: In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Abstract: Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

Abstract: Embodiments of the present disclosure relates to method of forming trench and via features using dielectric and metal mask layers. Particularly, embodiments of present disclosure provide a hard mask stack including a first dielectric mask layer, and second dielectric mask layer and a metal mask layer, wherein the first dielectric mask layer and second dielectric mask layer have a high etch selectivity.

Abstract: A semiconductor structure and method for forming a semiconductor structure includes formation of a recess in a metal layer during the fabrication process to provide process improvements and a conductive via with reduced contact resistance. The semiconductor structure includes a dielectric layer, a metal layer, an etch stop layer, and a conductive via. The top surface of the dielectric layer extends above a top surface of the metal layer, and a bottom surface of the conductive via extends below the top surface of the dielectric layer.

Abstract: An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.

Abstract: Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

Abstract: A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

Abstract: An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Abstract: Methods for manufacturing semiconductor structures are provided. The method includes forming a first masking layer over a substrate and forming a second masking layer over the first masking layer. The method includes forming a photoresist pattern over the second masking layer and patterning the second masking layer through the photoresist pattern. The method further includes diminishing the photoresist pattern and patterning the second masking layer and the first masking layer through the diminished photoresist pattern. The method further includes removing the diminished photoresist pattern and patterning the semiconductor substrate through the second masking layer and the first masking layer to form a fin structure. The method further includes forming a gate structure over the fin structure.

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.