Patents by Inventor Yi-Nien Su

Yi-Nien Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050233572
    Abstract: A method for forming a dual damascene interconnect structure provides an intermetal dielectric that includes a spin-on low-k dielectric material formed over a CVD low-k dielectric material. A via opening is formed by etching through the spin-on low-k dielectric material and the CVD low-k dielectric material and a plug material is introduced to fill the via opening. A highly selective trench etching operation etches a trench in the upper, spin-on low-k dielectric material and removes the plug material from the via without attacking the lower CVD low-k dielectric material to form the dual damascene opening which is then filled with a conductive interconnect material. The intermetal dielectric formed of multiple low-k dielectric layers provides advantageous electrical and mechanical properties.
    Type: Application
    Filed: April 14, 2004
    Publication date: October 20, 2005
    Inventors: Yi-Nien Su, Jyu-Horng Shieh
  • Patent number: 6828251
    Abstract: A method for plasma etching is disclosed with improved etching selectivity for a nitride containing DARC and a low-k dielectric layer. Plasma chemistry is controlled by adjusting a nitrogen to oxygen ratio to achieve improved etching selectivity in both nitride containing and low-k dielectric layers. Nitrogen to oxygen ratios are adjusted to control etching of for example, a DARC nitride containing layer, and Carbon to fluorine ratios are additionally adjusted to control etching in a low-k dielectric layer.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: December 7, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Nien Su, Jen-Cheng Liu, Li-Chih Chaio
  • Patent number: 6797627
    Abstract: A new method is provided for the removal of polymer, possibly mixed with copper oxide residue, from exposed surfaces after an etch stop layer has been removed. The exposed surfaces are treated with a first plasma etch followed by a DI water rinse after which a second plasma etch of the exposed surfaces is performed. By selecting the chemistry and the conditions for the first and the second plasma etch, polymer residues and formed copper oxide residues are removed from the exposed surfaces.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: September 28, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hsin-Ching Shih, Yi-Nien Su, Li-Te S. Lin, Li-Chie Chiao
  • Publication number: 20030155329
    Abstract: A method for plasma etching is disclosed with improved etching selectivity for a nitride containing DARC and a low-k dielectric layer. Plasma chemistry is controlled by adjusting a nitrogen to oxygen ratio to achieve improved etching selectivity in both nitride containing and low-k dielectric layers. Nitrogen to oxygen ratios are adjusted to control etching of for example, a DARC nitride containing layer, and Carbon to fluorine ratios are additionally adjusted to control etching in a low-k dielectric layer.
    Type: Application
    Filed: February 15, 2002
    Publication date: August 21, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Nien Su, Jen-Cheng Liu, Li-Chih Chao