Abstract: A flexible touch panel includes a display unit, a touch sensing unit and a protective layer. The touch sensing unit is bounded to the display unit, and includes two touch control circuit layers and a waveplate. The waveplate is disposed between two touch control circuit layers, and includes a first plane and a second plane opposite to the first plane. One of the touch control circuit layers is formed on the first plane. The protective layer is bounded to the touch sensing unit, and the touch sensing unit is disposed between the display unit and the protective layer.

Abstract: A power converting device includes a first and a second power module electrically coupled in parallel, a loop current limiting circuit and a driving circuit. A first and a second terminal of the loop current limiting circuit are coupled to the first and the second power module respectively. A third and a fourth terminal of the loop current limiting circuit are coupled to each other. The loop current limiting circuit includes a coupled differential-mode inductor, a first inductive unit and a second inductive unit. A first winding and a second winding of the coupled differential-mode inductor are coupled to the first and the second power modules respectively. The first and the second inductive units are coupled to the first and the second power modules respectively. The driving circuit is configured to output a driving signal to the first and the second power module according to a current detecting signal.

Abstract: A power converting device includes a first and a second power module electrically coupled in parallel, a loop current limiting circuit and a driving circuit. A first and a second terminal of the loop current limiting circuit are coupled to the first and the second power module respectively. A third and a fourth terminal of the loop current limiting circuit are coupled to each other. The loop current limiting circuit includes a coupled differential-mode inductor, a first inductive unit and a second inductive unit. A first winding and a second winding of the coupled differential-mode inductor are coupled to the first and the second power modules respectively. The first and the second inductive units are coupled to the first and the second power modules respectively. The driving circuit is configured to output a driving signal to the first and the second power module according to a current detecting signal.

Abstract: An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.

Abstract: An edge-dominant alignment method for use in an exposure scanner system is provided. The method includes the steps of: providing a wafer having a plurality of shot areas, wherein each shot area has a plurality of alignment marks; determining a first outer zone of the wafer, wherein the first outer zone includes a first portion of the shot areas along a first outer edge of the wafer; determining a scan path according to the shot areas of the first outer zone; and performing an aligning process to each shot area of the first outer zone according to the scan path and an alignment mark of each shot area of the first outer zone.

Abstract: A method for layoutless overlay control is provided. In some embodiments, a target layer covering a workpiece is patterned using a reticle. The patterning forms a plurality of exposure fields arranged according to a first exposure field layout. Alignment of the exposure fields relative to the workpiece is measured to generate displacement vectors. An inter-field model and an intra-field model are trained using the displacement vectors and a reference field layout. The intra-field model is transformed for use with a second exposure field layout, where the second exposure field layout is different than the first exposure field layout. Overlay corrections are generated based on the trained inter-field model and the transformed intra-field model.

Abstract: Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing the plurality of fields into an orthogonal field structure and two or more continuous field structures. A first number of alignment structure positions are measured within each field of the two or more continuous field structures, and a second number of alignment structure positions are measured within each field of the orthogonal field structure, the second number being greater than the first number. The feature or layer is then aligned to the previously formed feature or layer based upon the measured alignment structure positions of the two or more continuous field structures and the orthogonal field structure.

Abstract: Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs.

Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

Abstract: An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.

Abstract: A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies.

Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.

Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

Abstract: An edge-dominant alignment method for use in an exposure scanner system is provided. The method includes the steps of: providing a wafer having a plurality of shot areas, wherein each shot area has a plurality of alignment marks; determining a first outer zone of the wafer, wherein the first outer zone includes a first portion of the shot areas along a first outer edge of the wafer; determining a scan path according to the shot areas of the first outer zone; and performing an aligning process to each shot area of the first outer zone according to the scan path and an alignment mark of each shot area of the first outer zone.

Abstract: The invention provides a broadband cholesteric liquid crystal film, a method for fabricating the same, a polarization device employing the same, and high light efficiency liquid crystal display employing the same. The cholesteric liquid crystal film is a single-layer liquid crystal material structure, and has a top surface and a bottom surface. Further, the cholesteric liquid crystal film includes a first region, a second region, and a third region, and the first region is adjacent to the top surface of the cholesteric liquid crystal film, the third region is adjacent to the bottom surface of the cholesteric liquid crystal film, and the second region is located between the first and third regions, and the average helical pitch P1 of the first region and the average helical pitch P3 of the third region are both larger than the average helical pitch P2 of the second region.

Abstract: Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs.

Abstract: The invention provides a broadband cholesteric liquid crystal film, a method for fabricating the same, a polarization device employing the same, and high light efficiency liquid crystal display employing the same. The cholesteric liquid crystal film is a single-layer liquid crystal material structure, and has a top surface and a bottom surface. Further, the cholesteric liquid crystal film includes a first region, a second region, and a third region, and the first region is adjacent to the top surface of the cholesteric liquid crystal film, the third region is adjacent to the bottom surface of the cholesteric liquid crystal film, and the second region is located between the first and third regions, and the average helical pitch P1 of the first region and the average helical pitch P3 of the third region are both larger than the average helical pitch P2 of the second region.

Abstract: Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing the plurality of fields into an orthogonal field structure and two or more continuous field structures. A first number of alignment structure positions are measured within each field of the two or more continuous field structures, and a second number of alignment structure positions are measured within each field of the orthogonal field structure, the second number being greater than the first number. The feature or layer is then aligned to the previously formed feature or layer based upon the measured alignment structure positions of the two or more continuous field structures and the orthogonal field structure.

Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.

Abstract: A light efficiency enhancing optical device is disclosed, including a cholesteric liquid crystal film, a quarter wave plate disposed on a light out-going surface of the cholesteric liquid crystal film and an optical compensating film disposed on a light out-going surface of the quarter wave plate, wherein the optical compensating film includes a positive birefringence C-plate, and a composite optical compensating film with combination of the optical compensating film and the quarter wave plate has in-plane phase retardation R0 of 100 nm˜170 nm and out-of-plane phase retardation Rth of 0 nm˜400 nm.