Abstract: A power converter with a common DC power source includes a DC power source and at least two power modules. Each of the power modules is coupled with each other and coupled to the DC power source. Each of the power module includes a coupled inductive component coupled to the DC power source, a DC output conversion unit coupled to the coupled inductive component, and a capacitor group having a coupling point. By using the coupled inductive component, it is to solve the problem of return current between the power modules caused by coupling multiple coupling points to each other.

Abstract: An electronic device with heat sink is provided. The heat sink includes a base and fins. One side of the base has a first placement plane and a second placement plane. The electronic device includes a circuit board, a power module and transistors. The power module includes a power body and soldering legs, and the power body is attached to the first placement plane. The transistor has a transistor body and pins, and the transistor body is attached to the second placement plane. The circuit board is disposed at one side of the base formed with the first placement plane, and soldering legs of the power module and pins of the transistor are inserted on the circuit board. Thereby the heat sinks and the space which the circuit board occupied will be reduced for increasing the power density of the heat sink.

Abstract: A method of manufacturing a semiconductor structure includes providing a mask including a first substrate; a first mask layer disposed over the first substrate, including a plurality of first recesses extended through the first mask layer; a second mask layer disposed over the first mask layer and including a plurality of second recesses extended through the second mask layer; providing a second substrate including a photoresist disposed over the second substrate; and projecting a predetermined electromagnetic radiation through the mask towards the photoresist, wherein the first mask layer is at least partially transparent to the predetermined electromagnetic radiation, the second mask layer is opaque to the predetermined electromagnetic radiation, and at least a portion of the second mask layer is disposed between two of the plurality of second recesses.

Abstract: An inverter apparatus with overcurrent protection control includes a first terminal of a DC input terminal connected to an AC output terminal through a first switch element and a second switch element, and a second terminal of the DC input terminal connected to the AC output terminal through a fourth switch element and a third switch element. An intermediate potential terminal is connected to a fifth switch element and a sixth switch element, and connected to the AC output terminal through the fifth switch element and the second switch element, and connected to the AC output terminal through the sixth switch element and the third switch element. When the control unit determines that the inverter apparatus is in an overcurrent state, the control unit controls a sequence of turning off the inverter apparatus to be the second switch element, the first switch element, and the sixth switch element.

Abstract: An inverter apparatus with overcurrent protection control includes a first terminal of a DC input terminal connected to an AC output terminal through a first switch element and a second switch element, and a second terminal of the DC input terminal connected to the AC output terminal through a fourth switch element and a third switch element. An intermediate potential terminal is connected to a fifth switch element and a sixth switch element, and connected to the AC output terminal through the fifth switch element and the second switch element, and connected to the AC output terminal through the sixth switch element and the third switch element. When the control unit determines that the inverter apparatus is in an overcurrent state, the control unit controls a sequence of turning off the inverter apparatus to be the second switch element, the first switch element, and the sixth switch element.

Abstract: An optical film includes a plane and a plurality of dents. The plane has a normal, and the dents are formed on the plane. Each of the dents is asymmetric relative to the normal, wherein each of the dents includes an opening, and the maximum aperture of each of the dents is the caliber of the opening.

Abstract: A power bypass apparatus with a current-sharing function includes at least two bypass switch assemblies and a control unit. Each bypass switch assembly includes a controllable switch, a cooling unit, and a temperature detection unit. Each the temperature detection unit, correspondingly disposed to a heat-dissipating unit, detects a temperature value of the controllable switch to produce a temperature detection signal. The control unit receives the temperature detection signals and outputs at least two switch control signals to control at least one of the controllable switches or outputs at least two cooling unit control signals to control at least one of the cooling units, thus making currents flowing through the controllable switches identical. Accordingly, it is to increase overall efficiency of a power system and implement current-sharing function of the power system providing high power.

Abstract: A method for layoutless overlay control is provided. In some embodiments, a target layer covering a workpiece is patterned using a reticle. The patterning forms a plurality of exposure fields arranged according to a first exposure field layout. Alignment of the exposure fields relative to the workpiece is measured to generate displacement vectors. An inter-field model and an intra-field model are trained using the displacement vectors and a reference field layout. The intra-field model is transformed for use with a second exposure field layout, where the second exposure field layout is different than the first exposure field layout. Overlay corrections are generated based on the trained inter-field model and the transformed intra-field model.

Abstract: An optical film includes a plane and a plurality of dents. The plane has a normal, and the dents are formed on the plane. Each of the dents is asymmetric relative to the normal, wherein each of the dents includes an opening, and the maximum aperture of each of the dents is the caliber of the opening.

Abstract: A limiting viewing angle sheet comprises a substrate, a transparent layer and an opaque pattern. The transparent layer is disposed on the substrate, and comprises a top plane and a plurality of grooves formed on the top plane, wherein the width of each of the grooves is decreased from the top plane to the substrate. The opaque pattern is formed within the grooves, and comprises a top surface and a plurality of side planes, wherein the transparent layer is exposed from the top surface, and the side planes extend from the top surface. The opaque pattern comprised different included angels respectively between the top surface and two of the side planes.

Abstract: A flexible touch panel includes a display unit, a touch sensing unit and a protective layer. The touch sensing unit is bounded to the display unit, and includes two touch control circuit layers and a waveplate. The waveplate is disposed between two touch control circuit layers, and includes a first plane and a second plane opposite to the first plane. One of the touch control circuit layers is formed on the first plane. The protective layer is bounded to the touch sensing unit, and the touch sensing unit is disposed between the display unit and the protective layer.

Abstract: A power converting device includes a first and a second power module electrically coupled in parallel, a loop current limiting circuit and a driving circuit. A first and a second terminal of the loop current limiting circuit are coupled to the first and the second power module respectively. A third and a fourth terminal of the loop current limiting circuit are coupled to each other. The loop current limiting circuit includes a coupled differential-mode inductor, a first inductive unit and a second inductive unit. A first winding and a second winding of the coupled differential-mode inductor are coupled to the first and the second power modules respectively. The first and the second inductive units are coupled to the first and the second power modules respectively. The driving circuit is configured to output a driving signal to the first and the second power module according to a current detecting signal.

Abstract: A power converting device includes a first and a second power module electrically coupled in parallel, a loop current limiting circuit and a driving circuit. A first and a second terminal of the loop current limiting circuit are coupled to the first and the second power module respectively. A third and a fourth terminal of the loop current limiting circuit are coupled to each other. The loop current limiting circuit includes a coupled differential-mode inductor, a first inductive unit and a second inductive unit. A first winding and a second winding of the coupled differential-mode inductor are coupled to the first and the second power modules respectively. The first and the second inductive units are coupled to the first and the second power modules respectively. The driving circuit is configured to output a driving signal to the first and the second power module according to a current detecting signal.

Abstract: An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.

Abstract: An edge-dominant alignment method for use in an exposure scanner system is provided. The method includes the steps of: providing a wafer having a plurality of shot areas, wherein each shot area has a plurality of alignment marks; determining a first outer zone of the wafer, wherein the first outer zone includes a first portion of the shot areas along a first outer edge of the wafer; determining a scan path according to the shot areas of the first outer zone; and performing an aligning process to each shot area of the first outer zone according to the scan path and an alignment mark of each shot area of the first outer zone.

Abstract: A method for layoutless overlay control is provided. In some embodiments, a target layer covering a workpiece is patterned using a reticle. The patterning forms a plurality of exposure fields arranged according to a first exposure field layout. Alignment of the exposure fields relative to the workpiece is measured to generate displacement vectors. An inter-field model and an intra-field model are trained using the displacement vectors and a reference field layout. The intra-field model is transformed for use with a second exposure field layout, where the second exposure field layout is different than the first exposure field layout. Overlay corrections are generated based on the trained inter-field model and the transformed intra-field model.

Abstract: Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing the plurality of fields into an orthogonal field structure and two or more continuous field structures. A first number of alignment structure positions are measured within each field of the two or more continuous field structures, and a second number of alignment structure positions are measured within each field of the orthogonal field structure, the second number being greater than the first number. The feature or layer is then aligned to the previously formed feature or layer based upon the measured alignment structure positions of the two or more continuous field structures and the orthogonal field structure.

Abstract: Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs.

Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

Abstract: An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.