Patents by Inventor Yi-Ping Hsieh

Yi-Ping Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9164398
    Abstract: A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: October 20, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Yao Lee, Ying-Ying Wang, Yi-Ping Hsieh, Heng-Hsin Liu
  • Patent number: 9123583
    Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsien Lin, Kuo-Hung Chao, Yi-Ping Hsieh, Yen-Di Tsen, Jui-Chun Peng, Heng-Hsin Liu, Jong-I Mou
  • Publication number: 20150170904
    Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 18, 2015
    Inventors: Yen-Di TSEN, Yi-Ping HSIEH, Chen-Yen HUANG, Shin-Rung LU, Jong-I MOU
  • Publication number: 20150116686
    Abstract: An edge-dominant alignment method for use in an exposure scanner system is provided. The method includes the steps of: providing a wafer having a plurality of shot areas, wherein each shot area has a plurality of alignment marks; determining a first outer zone of the wafer, wherein the first outer zone includes a first portion of the shot areas along a first outer edge of the wafer; determining a scan path according to the shot areas of the first outer zone; and performing an aligning process to each shot area of the first outer zone according to the scan path and an alignment mark of each shot area of the first outer zone.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Yao LEE, Ying-Ying WANG, Yi-Ping HSIEH, Heng-Hsin LIU
  • Publication number: 20150110967
    Abstract: The invention provides a broadband cholesteric liquid crystal film, a method for fabricating the same, a polarization device employing the same, and high light efficiency liquid crystal display employing the same. The cholesteric liquid crystal film is a single-layer liquid crystal material structure, and has a top surface and a bottom surface. Further, the cholesteric liquid crystal film includes a first region, a second region, and a third region, and the first region is adjacent to the top surface of the cholesteric liquid crystal film, the third region is adjacent to the bottom surface of the cholesteric liquid crystal film, and the second region is located between the first and third regions, and the average helical pitch P1 of the first region and the average helical pitch P3 of the third region are both larger than the average helical pitch P2 of the second region.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 23, 2015
    Inventors: Hui-Lung KUO, Mei-Chih PENG, Yi-Ping HSIEH, Chin-Kai CHANG
  • Publication number: 20150042994
    Abstract: Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lee Yung-Yao, Ying Ying Wang, Yi-Ping Hsieh
  • Patent number: 8947620
    Abstract: The invention provides a broadband cholesteric liquid crystal film, a method for fabricating the same, a polarization device employing the same, and high light efficiency liquid crystal display employing the same. The cholesteric liquid crystal film is a single-layer liquid crystal material structure, and has a top surface and a bottom surface. Further, the cholesteric liquid crystal film includes a first region, a second region, and a third region, and the first region is adjacent to the top surface of the cholesteric liquid crystal film, the third region is adjacent to the bottom surface of the cholesteric liquid crystal film, and the second region is located between the first and third regions, and the average helical pitch P1 of the first region and the average helical pitch P3 of the third region are both larger than the average helical pitch P2 of the second region.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: February 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Hui-Lung Kuo, Mei-Chih Peng, Yi-Ping Hsieh, Chin-Kai Chang
  • Publication number: 20150015870
    Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 15, 2015
    Inventors: Chun-Hsien Lin, Kuo-Hung Chao, Yi-Ping Hsieh, Yen-Di Tsen, Jui-Chun Peng, Heng-Hsin Liu, Jong-I Mou
  • Publication number: 20150016943
    Abstract: Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing the plurality of fields into an orthogonal field structure and two or more continuous field structures. A first number of alignment structure positions are measured within each field of the two or more continuous field structures, and a second number of alignment structure positions are measured within each field of the orthogonal field structure, the second number being greater than the first number. The feature or layer is then aligned to the previously formed feature or layer based upon the measured alignment structure positions of the two or more continuous field structures and the orthogonal field structure.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 15, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ping Hsieh, Yung-Yao Lee, Ying Ying Wang, Shin-Rung Lu
  • Patent number: 8922740
    Abstract: A light efficiency enhancing optical device is disclosed, including a cholesteric liquid crystal film, a quarter wave plate disposed on a light out-going surface of the cholesteric liquid crystal film and an optical compensating film disposed on a light out-going surface of the quarter wave plate, wherein the optical compensating film includes a positive birefringence C-plate, and a composite optical compensating film with combination of the optical compensating film and the quarter wave plate has in-plane phase retardation R0 of 100 nm˜170 nm and out-of-plane phase retardation Rth of 0 nm˜400 nm.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: December 30, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Ping Hsieh, Hui-Lung Kuo, Jui-Fa Chang, Mei-Chih Peng, Yi-Chang Du
  • Publication number: 20140240706
    Abstract: A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies.
    Type: Application
    Filed: April 14, 2014
    Publication date: August 28, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Yao LEE, Ying-Ying WANG, Yi-Ping HSIEH, Heng-Hsin LIU
  • Publication number: 20120169960
    Abstract: The invention provides a broadband cholesteric liquid crystal film, a method for fabricating the same, a polarization device employing the same, and high light efficiency liquid crystal display employing the same. The cholesteric liquid crystal film is a single-layer liquid crystal material structure, and has a top surface and a bottom surface. Further, the cholesteric liquid crystal film includes a first region, a second region, and a third region, and the first region is adjacent to the top surface of the cholesteric liquid crystal film, the third region is adjacent to the bottom surface of the cholesteric liquid crystal film, and the second region is located between the first and third regions, and the average helical pitch P1 of the first region and the average helical pitch P3 of the third region are both larger than the average helical pitch P2 of the second region.
    Type: Application
    Filed: October 28, 2011
    Publication date: July 5, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hui-Lung Kuo, Mei-Chih Peng, Yi-Ping Hsieh, Chin-Kai Chang
  • Patent number: 8092026
    Abstract: An optical engine includes a receiving chamber and three light source modules. Each light source module includes a positioning board, a heat dissipating plate, and a light source unit. The heat dissipating plate is sandwiched between the light source unit and the positioning board and adhered to the corresponding light source unit. The light source unit is installed on the receiving chamber. The positioning board is matched with the light source unit and installed on the receiving chamber.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: January 10, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Yi-Ping Hsieh
  • Patent number: 8061849
    Abstract: A lens module includes a seat, a lens holder and a thermal dissipation structure. The seat includes a base plate and two sidewalls perpendicularly formed on a surface of the base plate. The lens holder is mounted on the seat between the two sidewalls. The thermal dissipation structure is mounted on the seat and thermally conducts with the lens holder for cooling the lens holder.
    Type: Grant
    Filed: December 25, 2008
    Date of Patent: November 22, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Yi-Ping Hsieh, Chien-Fu Chen
  • Patent number: 8052282
    Abstract: An electronic device includes a heat dissipation system and an operating system. The heat dissipation system includes a housing, a first heat dissipation module received in the housing, heat pipes extending from the first heat dissipation module through the housing. The operating system includes a dust-proof housing, a heat source and a heat dissipation device. The heat source is received in the dust-proof housing and generates heat. The cooling module is adhered to an outer surface of the dust-proof housing to be cooled and attaches the heat pipes to the first heat dissipation module. The outer surface of the dust-proof housing is adjacent to the housing. The heat pipes transfer heat from the operating system into the first heat dissipation module.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: November 8, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chien-Fu Chen, Yi-Ping Hsieh, Chung-Chen Chen
  • Patent number: 8023080
    Abstract: A high transmittance brightness enhanced optical element for backlight modules and liquid crystal display device is disclosed. The brightness enhanced polarizing optical element comprises a reflective polarizer film, a phase retardation film, and a polarization enhancement film. The reflective polarizer film provides a function of selectively reflecting right-handness circularly polarized light or left-handness circularly polarized light and will transmit the other one of them. The one was selectively reflected will be recombined with the light source or the backlight and re-direct toward the reflective polarizer. The portions of the reflective light will be recombined with the fresh light from the light source as above and the processes repeatedly. As a result, almost all of the light transmit the reflective polarizer and in the same circular polarization. The light is then transmitted the phase retardation film and converted to a polarized light with another optical axis.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: September 20, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Hui-Lung Kuo, Ping-Chen Chen, Yi-Ping Hsieh, Pao-Ju Hsieh, Yu-Hsun Wu
  • Patent number: 8007114
    Abstract: A projector includes a housing, a projection lens, a receiving member, an optical engine, a light source module, a heat sink, and a fan. The housing includes a bottom wall and four sidewalls, the bottom wall and the four sidewalls together define a receiving space. One of the sidewalls a number of first vents, the other three sidewalls define a number of second vents. The projection lens is located at an intersecting corner of the sidewalls. The receiving member includes a first receiving portion and a second receiving portion. The optical engine is received in the second receiving portion. The light source module is received in the first receiving portion. The heat sink is located at an intersecting corner of the sidewalls. The fan is located at an intersecting corner of the sidewalls.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: August 30, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chien-Fu Chen, Yi-Ping Hsieh, Tsung-Je Chiu
  • Publication number: 20110141406
    Abstract: A low color variation optical device is provided. The optical device includes a cholesteric liquid crystal film, a first phase retardation film disposed above the cholesteric liquid crystal film and a second phase retardation film disposed below the cholesteric liquid crystal film, wherein the second phase retardation film includes a plurality of molecules with a tilted and twisted arrangement. The invention also provides a backlight module and a liquid crystal display including a low color variation optical device.
    Type: Application
    Filed: April 9, 2010
    Publication date: June 16, 2011
    Applicant: Industrial Technology Research Institute
    Inventors: Ying-Jui Lin, Hui-Lung Kuo, Ping-Chen Chen, Mei-Chih Peng, Yi-Ping Hsieh
  • Publication number: 20100171921
    Abstract: A liquid crystal display (LCD) includes two glass substrates, a liquid crystal unit formed by sandwiching a liquid crystal layer between the two glass substrates, a first polarizing film, and a second polarizing film. In another example, the LCD further includes a diffuse reflective film formed on the other side of the second polarizing film. In another example, the second polarizing film is replaced by a reflective film. The liquid crystal layer is composed of an antiferroelectric (including intermediate antiferroelectric) smectic liquid crystal material, and a birefringence of the liquid crystal layer changes along with an electric field applied to the liquid crystal layer.
    Type: Application
    Filed: January 6, 2009
    Publication date: July 8, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Alexei Removich Khokhlov, Alexander Vyacheslavovich Emelyanenko, Evgeny Pavlovich Pozhidaev, Nikolay Mikhailovich Shtykov, Vadim Evgenievich Molkin, Hui-Lung Kuo, Yi-Ping Hsieh
  • Publication number: 20100110388
    Abstract: A light-source module includes a casing, and a number of light-source units. The casing defines a number of receiving holes on the walls thereof corresponding to the light-source units. Each light-source unit is received in a corresponding receiving hole. Each light-source unit includes a light source, a converging lens disposed on the optical path of the light emitted from the light source, and a spacer spaced the light source and the converging lens.
    Type: Application
    Filed: December 22, 2008
    Publication date: May 6, 2010
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: YI-PING HSIEH