Patents by Inventor Yi-Shien Mor
Yi-Shien Mor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130228876Abstract: System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions.Type: ApplicationFiled: March 2, 2012Publication date: September 5, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Shien Mor, Hsiao-Chu Chen, Mu-Chi Chiang
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Patent number: 8524588Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function.Type: GrantFiled: June 26, 2009Date of Patent: September 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Donald Y. Chao, Yi-Shien Mor, Kuo-Tai Huang
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Publication number: 20130207265Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.Type: ApplicationFiled: February 10, 2012Publication date: August 15, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chu LIU, Yi-Shien MOR, Kuei-Shun CHEN, Yu Lun LIU, Han-Hsun CHANG, Shiao-Chian YEH
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Publication number: 20130187206Abstract: A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.Type: ApplicationFiled: January 24, 2012Publication date: July 25, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Shien Mor, Hsiao-Chu Chen, Mu-Chi Chiang
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Publication number: 20130181300Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region.Type: ApplicationFiled: January 16, 2012Publication date: July 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Shien Mor, Hsiao-Chu Chen, Mu-Chi Chiang
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Patent number: 8461654Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.Type: GrantFiled: October 11, 2011Date of Patent: June 11, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yuan Wu, Yi-Shien Mor, Chih-Tang Peng, Chiung-Han Yeh, Kong-Beng Thei, Harry Chuang, Mong-Song Liang
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Patent number: 8383502Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.Type: GrantFiled: July 20, 2011Date of Patent: February 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin, Yi-Shien Mor, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen
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Patent number: 8349680Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.Type: GrantFiled: August 6, 2009Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Harry Chuang, Ryan Chia-Jen Chen, Su-Chen Lai, Yi-Shien Mor, Yi-Hsing Chen, Gary Shen, Yu Chao Lin
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Publication number: 20120025329Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.Type: ApplicationFiled: October 11, 2011Publication date: February 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yuah Wu, Yi-Shien Mor, Chih-Tang Peng, Chiung-Han Yeh, Kong-Beng Thei, Harry Chuang, Mong-Song Liang
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Publication number: 20110275212Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.Type: ApplicationFiled: July 20, 2011Publication date: November 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin, Yi-Shien Mor, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen
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Patent number: 8048752Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.Type: GrantFiled: July 24, 2008Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yuan Wu, Yi-Shien Mor, Chih-Tang Peng, Chiung-Han Yeh, Kong-Beng Thei, Harry Chuang, Mong-Song Liang
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Patent number: 8003507Abstract: The present disclosure provides a method of fabricating a semiconductor device.Type: GrantFiled: June 4, 2009Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin, Yi-Shien Mor, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen
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Patent number: 7947591Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.Type: GrantFiled: April 9, 2008Date of Patent: May 24, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Peng-Fu Hsu, Fong-Yu Yen, Yi-Shien Mor, Huan-Just Lin, Ying Jin, Hun-Jan Tao
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Publication number: 20100048013Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.Type: ApplicationFiled: August 6, 2009Publication date: February 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kong-Beng Thei, Harry Chuang, Ryan Chia-Jen Chen, Su-Chen Lai, Yi-Shien Mor, Yi-Hsing Chen, Gary Shen, Y. C. Lin
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Publication number: 20100038721Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function.Type: ApplicationFiled: June 26, 2009Publication date: February 18, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Donald Y. Chao, Yi-Shien Mor, Kuo-Tai Huang
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Publication number: 20100041223Abstract: The present disclosure provides a method of fabricating a semiconductor device.Type: ApplicationFiled: June 4, 2009Publication date: February 18, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin, Yi-Shien Mor, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen
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Publication number: 20100022061Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.Type: ApplicationFiled: July 24, 2008Publication date: January 28, 2010Inventors: Ming-Yuan Wu, Yi-Shien Mor, Chih-Tang Peng, Chiung-Han Yeh, Kong-Beng Thei, Harry Chuang, Mong-Song Liang
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Publication number: 20080188044Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.Type: ApplicationFiled: April 9, 2008Publication date: August 7, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peng-Fu Hsu, Fong-Yu Yen, Yi-Shien Mor, Huan-Just Lin, Ying Jin, Hun-Jan Tao
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Patent number: 7382028Abstract: A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the increased grain size.Type: GrantFiled: April 15, 2005Date of Patent: June 3, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung-Heng Hsieh, Chien-Li Cheng, Yi-Shien Mor, Yung-Shun Chen
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Patent number: 7378713Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.Type: GrantFiled: October 25, 2006Date of Patent: May 27, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Peng-Fu Hsu, Fong-Yu Yen, Yi-Shien Mor, Huan-Just Lin, Ying Jin, Hun-Jan Tao