Patents by Inventor Yi-Tzu Chen
Yi-Tzu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929109Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.Type: GrantFiled: April 25, 2023Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
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Publication number: 20230395122Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.Type: ApplicationFiled: August 4, 2023Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
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Publication number: 20230368826Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Yi-Tzu CHEN, Ching-Wei WU, Hau-Tai SHIEH, Hung-Jen LIAO, Fu-An WU, He-Zhou WAN, XiuLi YANG
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Patent number: 11763873Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.Type: GrantFiled: May 25, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
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Publication number: 20230267989Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.Type: ApplicationFiled: April 25, 2023Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
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Publication number: 20230245677Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.Type: ApplicationFiled: January 30, 2023Publication date: August 3, 2023Inventors: Yi-Tzu Chen, Hau-Tai Shieh, Che-Ju Yeh
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Patent number: 11715505Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.Type: GrantFiled: July 29, 2022Date of Patent: August 1, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITEDInventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou Wan, XiuLi Yang
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Patent number: 11682453Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. A control circuit includes a first transistor, an inverter coupled to the first transistor, and a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal. The second transistor is coupled to the inverter. The first source/drain terminal of the second transistor is coupled in series to the first transistor. The second source/drain terminal is coupled to a decoder driver circuit. The second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.Type: GrantFiled: June 30, 2021Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Anjana Singh, Cheng Hung Lee, Hau-Tai Shieh, Yi-Tzu Chen
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Patent number: 11670362Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.Type: GrantFiled: March 4, 2022Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
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Patent number: 11568121Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.Type: GrantFiled: April 9, 2021Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Tzu Chen, Hau-Tai Shieh, Che-Ju Yeh
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Patent number: 11540620Abstract: A hair comb is provided and comprises a base assembly, a comb teeth assembly, and a cover unit. The base assembly comprises a first surface and a second surface opposite to each other. The comb teeth assembly is placed at the first surface of the base assembly. The cover unit is detachably mounted on the second surface. The cover unit comprises a third surface and a fourth surface opposite to each other. The third surface faces the second surface and the fourth surface is decorated by decorative patterns or figures.Type: GrantFiled: December 1, 2020Date of Patent: January 3, 2023Assignee: Zhongshan Yingliang Health Technology Co., Ltd.Inventor: Yi-Tzu Chen
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Patent number: 11503900Abstract: A mist spraying hair brush with retractable bristles includes a brush body, an actuating shaft, a mist spraying assembly, and a housing containing these components. The actuating shaft has a bended portion. When the actuating shaft is rotated and the bended portion pushes the brush body, multiple bristles of the brush body extend out of the housing. The mist spraying assembly has an electric oscillation assembly and an injection portion. The injection portion communicates with the oscillation assembly, such that liquid flows to the oscillation assembly via the injection portion and is atomized into spray. Then the spray flows out of the housing. The mist spraying hair brush with retractable bristles is small in size and is convenient in storage. Moreover, the multiple bristles can retract into the housing, so the multiple bristles will not be bended when carried in a bag full of objects.Type: GrantFiled: March 18, 2020Date of Patent: November 22, 2022Assignee: Zhongshan Yingliang Health Technology Co., Ltd.Inventor: Yi-Tzu Chen
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Publication number: 20220366950Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Yi-Tzu CHEN, Ching-Wei WU, Hau-Tai SHIEH, Hung-Jen LIAO, Fu-An WU, He-Zhou WAN, XiuLi YANG
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Patent number: 11468929Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.Type: GrantFiled: April 20, 2021Date of Patent: October 11, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITEDInventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou Wan, XiuLi Yang
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Publication number: 20220284941Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
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Publication number: 20220277781Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.Type: ApplicationFiled: April 20, 2021Publication date: September 1, 2022Inventors: Yi-Tzu CHEN, Ching-Wei WU, Hau-Tai SHIEH, Hung-Jen LIAO, Fu-An WU, He-Zhou WAN, XiuLi YANG
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Patent number: 11406866Abstract: An exercise device for deep squat and body stretch has a device body, a damping assembly, and a pedal set. The device body has a base. The damping assembly is disposed on the base, and has a tube, a pneumatic cylinder which has multiple positioning through holes, and a seat. The pneumatic cylinder is mounted in the tube. An adjusting component is able to extend through the tube and is mounted with one of the positioning through holes. The seat is connected to the pneumatic cylinder for height adjustment. The pedal set is assembled on the device body, and has two pedals rotatably mounted on the device body.Type: GrantFiled: November 6, 2020Date of Patent: August 9, 2022Assignee: Zhongshan Yingliang Health Technology Co., Ltd.Inventor: Yi-Tzu Chen
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Publication number: 20220199145Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.Type: ApplicationFiled: March 4, 2022Publication date: June 23, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
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Patent number: 11361810Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.Type: GrantFiled: November 24, 2020Date of Patent: June 14, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
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Patent number: 11361812Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.Type: GrantFiled: October 27, 2020Date of Patent: June 14, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao