Patents by Inventor Yi-Tzu Chen

Yi-Tzu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220284941
    Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.
    Type: Application
    Filed: May 25, 2022
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
  • Publication number: 20220277781
    Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Application
    Filed: April 20, 2021
    Publication date: September 1, 2022
    Inventors: Yi-Tzu CHEN, Ching-Wei WU, Hau-Tai SHIEH, Hung-Jen LIAO, Fu-An WU, He-Zhou WAN, XiuLi YANG
  • Patent number: 11406866
    Abstract: An exercise device for deep squat and body stretch has a device body, a damping assembly, and a pedal set. The device body has a base. The damping assembly is disposed on the base, and has a tube, a pneumatic cylinder which has multiple positioning through holes, and a seat. The pneumatic cylinder is mounted in the tube. An adjusting component is able to extend through the tube and is mounted with one of the positioning through holes. The seat is connected to the pneumatic cylinder for height adjustment. The pedal set is assembled on the device body, and has two pedals rotatably mounted on the device body.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: August 9, 2022
    Assignee: Zhongshan Yingliang Health Technology Co., Ltd.
    Inventor: Yi-Tzu Chen
  • Patent number: 11404361
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 2, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Publication number: 20220216185
    Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu, Ping-Tzu Chen, Che-Wei Chen
  • Publication number: 20220208651
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard contact disposed within a dielectric structure on a substrate. An oversized contact is disposed within the dielectric structure and is laterally separated from the standard contact. The oversized contact has a larger width than the standard contact. An interconnect wire vertically contacts the oversized contact. A through-substrate via (TSV) vertically extends through the substrate. The TSV physically and vertically contacts the oversized contact or the interconnect wire. The TSV vertically overlaps the oversized contact or the interconnect wire over a non-zero distance.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 30, 2022
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu, Ping-Tzu Chen
  • Publication number: 20220199145
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Application
    Filed: March 4, 2022
    Publication date: June 23, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Patent number: 11361812
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Patent number: 11361810
    Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
  • Publication number: 20220167737
    Abstract: A hair comb is provided and comprises a base assembly, a comb teeth assembly, and a cover unit. The base assembly comprises a first surface and a second surface opposite to each other. The comb teeth assembly is placed at the first surface of the base assembly. The cover unit is detachably mounted on the second surface. The cover unit comprises a third surface and a fourth surface opposite to each other. The third surface faces the second surface and the fourth surface is decorated by decorative patterns or figures.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 2, 2022
    Inventor: YI-TZU CHEN
  • Publication number: 20220143458
    Abstract: An exercise device for deep squat and body stretch has a device body, a damping assembly, and a pedal set. The device body has a base. The damping assembly is disposed on the base, and has a tube, a pneumatic cylinder which has multiple positioning through holes, and a seat. The pneumatic cylinder is mounted in the tube. The adjusting component is able to extend through the tube and is mounted with one of the positioning through holes. The seat is connected to the pneumatic cylinder for height adjustment. The pedal set is assembled on the device body, and has two pedals rotatably mounted on the device body.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Inventor: YI-TZU CHEN
  • Publication number: 20220130446
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Publication number: 20210397773
    Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.
    Type: Application
    Filed: April 9, 2021
    Publication date: December 23, 2021
    Inventors: Yi-Tzu Chen, Hau-Tai Shieh, Che-Ju Yeh
  • Publication number: 20210327499
    Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. A control circuit includes a first transistor, an inverter coupled to the first transistor, and a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal. The second transistor is coupled to the inverter. The first source/drain terminal of the second transistor is coupled in series to the first transistor. The second source/drain terminal is coupled to a decoder driver circuit. The second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Anjana Singh, Cheng Hung Lee, Hau-Tai Shieh, Yi-Tzu Chen
  • Publication number: 20210241811
    Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.
    Type: Application
    Filed: November 24, 2020
    Publication date: August 5, 2021
    Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
  • Patent number: 11056182
    Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. A control circuit includes a first transistor, an inverter coupled to the first transistor, and a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal. The second transistor is coupled to the inverter. The first source/drain terminal of the second transistor is coupled in series to the first transistor. The second source/drain terminal is coupled to a decoder driver circuit. The second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Anjana Singh, Cheng Hung Lee, Hau-Tai Shieh, Yi-Tzu Chen
  • Publication number: 20210161285
    Abstract: A mist spraying hair brush with retractable bristles includes a brush body, an actuating shaft, a mist spraying assembly, and a housing containing these components. The actuating shaft has a bended portion. When the actuating shaft is rotated and the bended portion pushes the brush body, multiple bristles of the brush body extend out of the housing. The mist spraying assembly has an electric oscillation assembly and an injection portion. The injection portion communicates with the oscillation assembly, such that liquid flows to the oscillation assembly via the injection portion and is atomized into spray. Then the spray flows out of the housing. The mist spraying hair brush with retractable bristles is small in size and is convenient in storage. Moreover, the multiple bristles can retract into the housing, so the multiple bristles will not be bended when carried in a bag full of objects.
    Type: Application
    Filed: March 18, 2020
    Publication date: June 3, 2021
    Inventor: Yi-Tzu Chen
  • Publication number: 20200279603
    Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. A control circuit includes a first transistor, an inverter coupled to the first transistor, and a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal. The second transistor is coupled to the inverter. The first source/drain terminal of the second transistor is coupled in series to the first transistor. The second source/drain terminal is coupled to a decoder driver circuit. The second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Inventors: Anjana Singh, Cheng Hung Lee, Hau-Tai Shieh, Yi-Tzu Chen
  • Patent number: 10658026
    Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. An inverter within a pre-decoder circuit receives a first input of a clocked address. The inverter determines an output based on the clocked address. An electrical load of a decoder driver circuit of the SRAM device is modified based on the output. Current to a transistor coupled at a common node is provided. The transistor is configured to electrically couple a plurality of transistors of the decoder driver circuit within the SRAM device.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Anjana Singh, Cheng Hung Lee, Hau-Tai Shieh, Yi-Tzu Chen
  • Patent number: D941589
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: January 25, 2022
    Assignee: Zhongshan Yingliang Health Technology Co., Ltd
    Inventor: Yi-Tzu Chen