Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: In at least one embodiment, a multiplexer has a plurality of sub-circuits, and each of the plurality of sub-circuits has a first transistor, a second transistor, and a third transistor. Drains of the first transistors are coupled with a first terminal of a fourth transistor, and drains of the second transistors are coupled with a second terminal of the fourth transistor. In at least one embodiment, a method of outputting data using the multiplexer includes turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information. The second transistor of a non-selected one of the plurality of sub-circuits is turned off. The fourth transistor is turned on responsive to the clock signal.

Abstract: A multifunctional linked fitness equipment has an elongated bottom, a seat stand, a front support frame seat pivotally mounted on a front end of the elongated bottom, a rear support frame seat pivotally mounted on a rear end of the seat stand, a link pivotally mounted between the front support frame seat and the rear support frame seat, a front support frame pivotally mounted on the elongated bottom and the front support frame seat, a rear support frame pivotally mounted on the elongated bottom and the rear support frame seat, and at least one resilient member mounted between the rear support frame seat and the elongated bottom. By combining or detaching the front support frame, the rear support frame or the seat stand with or from positioning pins, the fitness equipment can be utilized to selectively exercise the abdominal muscles and the legs based on the users' demand.

Abstract: An adjustable elliptical trainer has a base, two driving brackets, two handles, two pedal assemblies and an adjustment assembly. The base has a transmission wheel mounted rotatably thereon. The driving brackets are connected respectively to the transmission wheel. The handles are connected pivotally and respectively to the driving brackets. The pedal assemblies are mounted at opposite sides of the transmission wheels. The adjustment assembly is mounted on the front end of the base and has two guiding rods and a guiding bracket. The guiding rods are mounted on the base. The guiding bracket is connected to the transmission wheel and mounted slidably on the guiding rods. The adjustment assembly allows the pedal assemblies to move along two different elliptical motion paths.

Abstract: An oscillator includes a positive power supply node for providing a positive power supply voltage; a capacitor; and a constant current source providing a first constant current and coupled to the positive power supply node. The first constant current is independent from the positive power supply node. The oscillator also includes a charging current source configured to provide a second constant current to charge the capacitor, wherein the second constant current mirrors the first constant current. The oscillator further includes a constant current source inverter having a third constant current mirroring the first constant current. The constant current source inverter is configured to control the oscillator to transition state at a constant state transition voltage.

Abstract: A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line.

Abstract: A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.

Abstract: A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.

Abstract: A push-up exerciser has a base, two handgrips, a connecting rod having two ends respectively connected pivotally to the base and a supporter, at least one resilient element connected to the connecting rod and the supporter, a roller pivotally mounted on a lower end of the supporter, and a pad pivotally mounted on an upper end of the supporter. A user places his/her abdomen on the pad, grasps the handgrips and then bends or straightens his/her arms to perform push-ups. Since the at least one resilient element tends to pull the supporter and the connecting rod so the pad tends to support the abdomen of the user, load applied to the arms of the user is reduced. The push-up exerciser has simplified structure, low manufacturing cost and helps the user to safely perform push-ups.

Abstract: A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.

Abstract: A multifunctional linked fitness equipment has an elongated bottom, a seat stand, a front support frame seat pivotally mounted on a front end of the elongated bottom, a rear support frame seat pivotally mounted on a rear end of the seat stand, a link pivotally mounted between the front support frame seat and the rear support frame seat, a front support frame pivotally mounted on the elongated bottom and the front support frame seat, a rear support frame pivotally mounted on the elongated bottom and the rear support frame seat, and at least one resilient member mounted between the rear support frame seat and the elongated bottom. By combining or detaching the front support frame, the rear support frame or the seat stand with or from positioning pins, the fitness equipment can be utilized to selectively exercise the abdominal muscles and the legs based on the users' demand.

Abstract: A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.

Abstract: A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation.

Abstract: An abdominal exercise device has a base, a seat mounted on the base, a front frame rotatably on a front of the base, a rear frame rotatably mounted on a rear of the base, a connecter connected pivotally to the front frame and the rear frame, an adjusting assembly mounted on the base and at least one resilient element connected to the rear frame and adjusting assembly. The at least one resilient element pulls the rear frame along with the connecter and the front frame to assist in performing sit-ups so abdominal muscles of a user using the abdominal exercise device is trained.

Abstract: Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), the ICL outputting a logic low value if the a difference between the a voltage on the BL and a voltage on the BLB exceeds a threshold. Sensing the voltages includes providing at least a first and a second pull down field effect transistor (FET) each having a channel coupled between the first and second output nodes and a ground node, respectively, in a cross coupled arrangement, wherein the second pull down FET has a channel width that is greater than a channel width of the first pull down FET. Additional methods are disclosed.

Abstract: A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.

Abstract: A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line.

Abstract: An abdominal exercise device has a base, a seat mounted on the base, a front frame rotatably on a front of the base, a rear frame rotatably mounted on a rear of the base, a connecter connected pivotally to the front frame and the rear frame, an adjusting assembly mounted on the base and at least one resilient element connected to the rear frame and adjusting assembly. The at least one resilient element pulls the rear frame along with the connecter and the front frame to assist in performing sit-ups so abdominal muscles of a user using the abdominal exercise device is trained.