Patents by Inventor Yi-Tzu Chen
Yi-Tzu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9275721Abstract: Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.Type: GrantFiled: July 30, 2010Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Chen, Bin-Hau Lo, Tsai-Hsin Lai, Pey-Huey Chen, Hau-Tai Shieh
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Publication number: 20150352399Abstract: A running machine with a pulling rope has a treadmill and a rope assembly. The rope assembly is mounted on the treadmill and has a housing and at least one rope set mounted in the housing. Each of the at least one rope set has a pulling rope. An end of the pulling rope is secured in the housing. Another end of the pulling rope protrudes out of the housing and is connected to a grip. The pulling rope is resiliently retracted toward the housing. When a user is exercising on the running machine, one of two hands of the user holds the at least one grip and swings naturally to pull the pulling rope. Resilient restoring force of the pulling ropes provides resistance to the user pulling the pulling ropes. Accordingly, an upper body and a lower body of the user can be trained simultaneously.Type: ApplicationFiled: June 6, 2014Publication date: December 10, 2015Inventor: YI-TZU CHEN
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Patent number: 9208857Abstract: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.Type: GrantFiled: April 30, 2014Date of Patent: December 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Chen, Wei-jer Hsieh, Tsai-Hsin Lai, Ling-Fang Hsu, Hau-Tai Shieh
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Publication number: 20150279450Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: ApplicationFiled: June 12, 2015Publication date: October 1, 2015Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-yung Jonathan Chang
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Patent number: 9148132Abstract: A method of providing an oscillating signal, comprising providing a first constant current flowing from a positive power supply node, the first constant current independent of a variation in a positive power supply node voltage, providing a second constant current flowing from a positive power supply node to a second electrode of a capacitor, a first electrode of the capacitor connected directly to the positive power supply node, the second constant current mirroring the first constant current and charging the capacitor by reducing a voltage across the capacitor. A third constant current is provided flowing from the positive power supply node through a first NMOS transistor and mirroring the first constant current, the first NMOS transistor having a gate connected directly to the second electrode of the capacitor and an oscillating signal generated by turning on the first NMOS transistor when the capacitor reaches a predetermined voltage level.Type: GrantFiled: August 15, 2013Date of Patent: September 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yi-Tzu Chen
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Publication number: 20150206555Abstract: A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.Type: ApplicationFiled: January 21, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-I YANG, Yi-Tzu CHEN, Cheng-Jen CHANG, Geng-Cing LIN, Yu-Hao HU
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Patent number: 9058899Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: GrantFiled: November 18, 2013Date of Patent: June 16, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-Yung Jonathan Chang
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Publication number: 20150109847Abstract: A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.Type: ApplicationFiled: October 23, 2013Publication date: April 23, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hao HU, Yi-Tzu CHEN, Hao-I YANG, Cheng-Jen CHANG, Geng-Cing LIN
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Patent number: 9007851Abstract: Some embodiments relate to a sense amplifier output buffer configured to buffer an output of a sense amplifier. The sense amplifier output buffer includes a first pull-up element having a source coupled to a first DC supply terminal and having a drain coupled to an output terminal of the sense amplifier output buffer. A first pull-down element is in series with the first pull-up element and has a source coupled to a second DC supply terminal and has a drain coupled to the output terminal. A miller capacitance decoupling circuit is coupled between the drain of the first pull-up element and the drain of the first pull-down element. The miller capacitance decoupling circuit is configured to decouple miller capacitance associated with the drains of the pull-up and pull-down elements from the output terminal. Other embodiments are also disclosed.Type: GrantFiled: January 30, 2013Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Yuan Chen, Hau-Tai Shieh, Yi-Tzu Chen, Hong-Chen Cheng
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Publication number: 20150063039Abstract: A circuit includes stacked memory arrays and a control circuit. The stacked memory arrays includes a first layer and a second layer. The control circuit is configured to receive a first address in the first layer; cause the second layer to be enabled for accessing; and provide a second row address for accessing the second layer.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: CHIEN-YUAN CHEN, CHIEN-YU HUANG, YI-TZU CHEN, HAU-TAI SHIEH
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Patent number: 8958237Abstract: An apparatus and method for executing a write operation in a static random access memory (SRAM) array including memory cells that are coupled to a plurality of word lines and to a plurality of bit lines are provided. A clock signal is generated to start a write operation. A pulse is generated on the plurality of word lines in response to the clock signal. An operation voltage of the SRAM array is lowered for a period of time during the write operation. The period of time is controlled and the pulse is ended using a tracking circuit. The tracking circuit includes a plurality of tracking memory cells. The plurality of tracking memory cells have a timing characteristic that emulates a timing characteristic of the SRAM array during the write operation. The tracking circuit controls the period of time and ends the pulse based on the emulated timing characteristic.Type: GrantFiled: November 13, 2013Date of Patent: February 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hao-I Yang, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu, Chia-Hao Hsu
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Patent number: 8947953Abstract: Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a writeable voltage state, such that a potential of the bit cell can be overcome by the write operation. A voltage detector sends a reset signal to the pulse generator based upon the pulse generator lowering the internal voltage level past a reset trigger level. Responsive to receiving the reset signal, the pulse generator initializes charging of the internal voltage level to an original voltage level. In this way, the lowering of the internal voltage level is controlled so that one or more other bit cells are not affected (e.g., suffer data retention failure) by the relatively lower internal voltage level.Type: GrantFiled: December 30, 2012Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei Min Chan, Yi-Tzu Chen, Wei-Cheng Wu, Yen-Huei Chen, Hau-Tai Shieh
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Patent number: 8840529Abstract: An adjustable elliptical trainer has a base, two driving brackets, two handles, two pedal assemblies and an adjustment assembly. The base has a transmission wheel mounted rotatably thereon. The driving brackets are connected respectively to the transmission wheel. The handles are connected pivotally and respectively to the driving brackets. The pedal assemblies are mounted at opposite sides of the transmission wheels. The adjustment assembly is mounted on the front end of the base and has two guiding rods and a guiding bracket. The guiding rods are mounted on the base. The guiding bracket is connected to the transmission wheel and mounted slidably on the guiding rods. The adjustment assembly allows the pedal assemblies to move along two different elliptical motion paths.Type: GrantFiled: March 14, 2012Date of Patent: September 23, 2014Inventor: Yi-Tzu Chen
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Publication number: 20140233303Abstract: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.Type: ApplicationFiled: April 30, 2014Publication date: August 21, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Tzu Chen, Wei-jer Hsieh, Tsai-Hsin Lai, Ling-Fang Hsu, Hau-Tai Shieh
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Publication number: 20140221179Abstract: A rope pulling exercise apparatus with variable resistance has a main supporting frame, a rotary cylinder assembly pivotally mounted on the main supporting frame, a rotary wheel pivotally mounted on the main supporting frame, a driving device and a resistance generating device. The rotary cylinder assembly has a pull-rope wrapped around a rotary cylinder. The driving device has a driving wheel coaxially mounted on the rotary cylinder, a driven wheel coaxially mounted on the rotary wheel, aligning with the driving wheel and being smaller than the driving wheel in radius, and a transmission belt mounted around the driving wheel and the driven wheel. The resistance generating device selectively resists rotation of the rotary wheel. The rope pulling exercise apparatus provides a user one more option on choosing fitness equipments, and increases the user's desire on exercising.Type: ApplicationFiled: February 1, 2013Publication date: August 7, 2014Inventor: Yi-Tzu Chen
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Publication number: 20140211570Abstract: Some embodiments relate to a sense amplifier output buffer configured to buffer an output of a sense amplifier. The sense amplifier output buffer includes a first pull-up element having a source coupled to a first DC supply terminal and having a drain coupled to an output terminal of the sense amplifier output buffer. A first pull-down element is in series with the first pull-up element and has a source coupled to a second DC supply terminal and has a drain coupled to the output terminal. A miller capacitance decoupling circuit is coupled between the drain of the first pull-up element and the drain of the first pull-down element. The miller capacitance decoupling circuit is configured to decouple miller capacitance associated with the drains of the pull-up and pull-down elements from the output terminal. Other embodiments are also disclosed.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Yuan Chen, Hau-Tai Shieh, Yi-Tzu Chen, Hong-Chen Cheng
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Publication number: 20140185363Abstract: Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a writeable voltage state, such that a potential of the bit cell can be overcome by the write operation. A voltage detector sends a reset signal to the pulse generator based upon the pulse generator lowering the internal voltage level past a reset trigger level. Responsive to receiving the reset signal, the pulse generator initializes charging of the internal voltage level to an original voltage level. In this way, the lowering of the internal voltage level is controlled so that one or more other bit cells are not affected (e.g., suffer data retention failure) by the relatively lower internal voltage level.Type: ApplicationFiled: December 30, 2012Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei Min Chan, Yi-Tzu Chen, Wei-Cheng Wu, Yen-Huei Chen, Hau-Tai Shieh
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Patent number: 8750053Abstract: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.Type: GrantFiled: June 9, 2011Date of Patent: June 10, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Chen, Wei-jer Hsieh, Tsai-Hsin Lai, Ling-Fang Hsu, Hau-Tai Shieh
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Publication number: 20140119104Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: ApplicationFiled: November 18, 2013Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Jonathan Tsung-Yung Chang
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Publication number: 20130328636Abstract: A method of providing an oscillating signal, comprising providing a first constant current flowing from a positive power supply node, the first constant current independent of a variation in a positive power supply node voltage, providing a second constant current flowing from a positive power supply node to a second electrode of a capacitor, a first electrode of the capacitor connected directly to the positive power supply node, the second constant current mirroring the first constant current and charging the capacitor by reducing a voltage across the capacitor. A third constant current is provided flowing from the positive power supply node through a first NMOS transistor and mirroring the first constant current, the first NMOS transistor having a gate connected directly to the second electrode of the capacitor and an oscillating signal generated by turning on the first NMOS transistor when the capacitor reaches a predetermined voltage level.Type: ApplicationFiled: August 15, 2013Publication date: December 12, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yi-Tzu Chen