Patents by Inventor Yi Wu

Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11913121
    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: February 27, 2024
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Yi Wu, Chun-Hung Lu
  • Patent number: 11914142
    Abstract: A method for generating virtual reality images and used in a light field near-eye display includes steps of: shifting a display image according to at least one change vector of a plurality of eye movement parameters, and calculating a compensation mask according to a simulated image and superimposing the compensation mask on a target image to generate a superimposed target image, wherein brightness distributions of the simulated image and the compensation mask are opposite to each other. The light field near-eye display is also provided. In this way, the light field near-eye display for generating virtual reality images and the method thereof can achieve the purpose of improving the uniformity of the image and expanding the eye box size.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: February 27, 2024
    Assignee: Coretronic Corporation
    Inventors: Chih-Hung Lu, Jui-Yi Wu
  • Patent number: 11912664
    Abstract: Provided herein are methods, systems, kits, and compositions useful for determining small molecule-protein interactions and protein-protein interactions. The photo-click tags provided herein can be conjugated to a small molecule or amino acid analog to provide compounds that can be integrated into a protein through photo-conjugation, allowing for identification of a small molecule-protein interaction or protein-protein interaction to elucidate the small molecules mechanism of action or the protein targeted by the small molecule. In some embodiments, the photo-click tags comprise a photo-conjugation moiety and a click chemistry handle, allowing for the attachment of various functional groups (e.g., affinity tags) to the small molecule or amino acid analog.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: February 27, 2024
    Assignee: President and Fellows of Harvard College
    Inventors: Christina M. Woo, Jinxu Gao, Yuka Amako, Chia Fu Chang, Zhi Lin, Hung-Yi Wu
  • Patent number: 11912708
    Abstract: The present disclosure provides compounds and pharmaceutically acceptable salt thereof, and methods of using the same. The compounds and methods have a range of utilities as therapeutics, diagnostics, and research tools. In particular, the subject compositions and methods are useful for reducing signaling output of oncogenic proteins.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: February 27, 2024
    Assignee: KUMQUAT BIOSCIENCES INC.
    Inventors: Baogen Wu, Pingda Ren, Zhiyong Chen, Yi Liu
  • Publication number: 20240064937
    Abstract: An immersion cooling system includes a work tank, a chip device, a microchannel device, a first communication pipeline, and a first heat exchange device. The work tank includes a fluid section. The chip device is in the fluid section and has an inlet and an outlet. The chip device includes a motherboard, a chip, and a cover. The motherboard has a main surface substantially parallel to a vertical line. The cover is on the motherboard. The chip is between the cover and the motherboard. The microchannel device is in the chip device. Two ends of the microchannel device are respectively in communication with the inlet and the outlet. The first communication pipeline and the first heat exchange device are in the fluid section. Two ends of the first communication pipeline are respectively in communication with the outlet and the first heat exchange device.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 22, 2024
    Inventors: Chia-Yi WU, Tsung-Han LI, Tai-Ying TU, Ting-Yu PAI
  • Publication number: 20240061711
    Abstract: A computing device, an operation method of the computing device, and a system on chip are provided. The computing device includes an operator and a resource allocation manager. The operator includes multiple arithmetic units. The resource allocation manager is coupled to the operator and allocates the arithmetic units to a deep learning accelerator and a vector processor for use according to an amount of calculation of the deep learning accelerator and an amount of calculation of the vector processor. The operator receives a first operation request and a second operation request from the deep learning accelerator and the vector processor respectively, uses a first arithmetic unit group of the arithmetic units to perform a calculation of the first operation request, and uses a second arithmetic unit group of the arithmetic units to perform a calculation of the second operation request according to an allocation result.
    Type: Application
    Filed: January 18, 2023
    Publication date: February 22, 2024
    Applicant: ITE Tech. Inc.
    Inventors: Tzu-Yi Wu, Ming-Hsun Sung
  • Publication number: 20240063177
    Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Shang-Yun Hou
  • Patent number: 11908885
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The i magnetic element is wider than the isolation element. The semiconductor device structure further includes a conductive line over the isolation element.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
  • Patent number: 11910621
    Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a substrate. A bottom electrode via opening is formed in the dielectric layer. A bottom electrode is formed in the bottom electrode via opening. The bottom electrode is etched back. A selector is formed in the bottom electrode via opening and over the bottom electrode. A memory layer is formed over the selector. A top electrode is formed over the memory layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jau-Yi Wu
  • Publication number: 20240057274
    Abstract: An electronic device including a metal back cover, a metal frame, a first radiator and a second radiator is provided. The metal frame includes a disconnected part and two connecting parts, the two connecting parts are located at two sides of the disconnected part, separated from the disconnected part and connected to the metal back cover. A U-shaped slot is formed between the disconnected part and the metal back cover, and between the disconnected part and the two connecting parts. The first radiator is located beside the disconnected part and includes a feeding end and a first connecting end away from the feeding end, and the first connecting end is connected to the disconnected part. The second radiator is located beside the disconnected part, and includes a ground end and a second connecting end opposite to each other. The ground end is connected to the metal back cover.
    Type: Application
    Filed: June 1, 2023
    Publication date: February 15, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Hau Yuen Tan, Chih-Wei Liao, Shih-Keng Huang, Wen-Hgin Chuang, Chia-Hong Chen, Lin-Hsu Chiang, Cheng-Kuan Lin, His-Yung Chen
  • Publication number: 20240057291
    Abstract: A piece of immersion liquid cooling equipment, which is adapted for an electronic device, includes a tank, a condenser, a cold plate, and a first pipe. The tank accommodates a first fluid, and the electronic device is immersed in the first fluid in the form of a liquid. The condenser is disposed in the tank and located above the first fluid in the form of a liquid. The cold plate is disposed in the tank and is in thermal contact with at least one high power commodity of the electronic device. The first pipe is disposed and extends between an exterior and an interior of the tank. The first pipe communicates with the condenser and the cold plate. The first pipe is configured to receive a second fluid to flow through the condenser and the cold plate. A heat dissipation method for an electronic device.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 15, 2024
    Applicant: Wiwynn Corporation
    Inventors: Tai-Ying Tu, Chia-Yi Wu, Tsung-Han Li, Ting-Yu Pai
  • Patent number: 11900784
    Abstract: An electronic device has pair(s) of conductive plates that is coupled to a housing and is electrically isolated by a dielectric material. The pair(s) of conductive plates is positioned to change relative orientation in relation to mechanical force that deforms the housing. Capacitive driver(s) is electrically coupled to pair(s) of conductive plates. A controller is communicatively coupled to the capacitive driver(s). The controller identifies a first capacitance of the pair(s) of conductive plates associated with the housing being in a normal state. The controller detects, via the capacitor driver(s), a change in capacitance from the first capacitance to a second capacitance of the pair(s) of conductive plates. The controller compares the change in capacitance to a threshold. In response to the change exceeding the threshold, the controller generates a notification.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: February 13, 2024
    Assignee: Motorola Mobility LLC
    Inventors: Rachid Alameh, Yi Wu, James P. Ashley, Zhengping Ji
  • Patent number: 11896641
    Abstract: A peptide composition and methods for slimming and/or for promoting the growth of probiotics using early harvested rice prebiotics are provided. The peptide composition or the early harvested rice prebiotics includes at least one peptide as set forth in: SEQ ID NO: 1, SEQ ID NO: 2, SEQ ID NO: 3, SEQ ID NO: 4, SEQ ID NO: 5, SEQ ID NO: 6, SEQ ID NO: 7 and SEQ, ID NO: 8.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: February 13, 2024
    Assignee: TCI CO., LTD.
    Inventors: Yung-Hsiang Lin, Pei-Yi Wu
  • Patent number: 11901295
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20240047313
    Abstract: A package structure includes a leadframe, at least two dies, at least one spacer and a plastic package material. The leadframe includes a die pad. The dies are disposed on the die pad of the leadframe. The spacer is disposed between at least one of the dies and the die pad. The plastic package material is disposed on the leadframe, and covers the dies. A first minimum spacing distance is between one of a plurality of edges of the spacer and one of a plurality of edges of the die pad, a second minimum spacing distance is between one of a plurality of edges of the dies and one of the edges of the die pad, and the first minimum spacing distance is larger than the second minimum spacing distance.
    Type: Application
    Filed: November 3, 2022
    Publication date: February 8, 2024
    Inventors: Cheng-Fu YU, Kai-Jih SHIH, Chi-Yi WU
  • Publication number: 20240042166
    Abstract: A semiconductor light-emitting device includes a bonding substrate, a multi-layered metal unit, and a semiconductor lighting unit. The bonding substrate includes an upper surface and a lower surface opposite to the upper surface. The multi-layered metal unit is disposed on the upper surface of the bonding substrate such that an exposed region of the upper surface of the bonding substrate is exposed from the multi-layered metal unit. The semiconductor lighting unit is disposed on the multi-layered metal unit opposite to the bonding substrate. A method for manufacturing the semiconductor light-emitting device is also disclosed.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 8, 2024
    Inventors: Weifan KE, Chun-Yi WU, Bing-xian CHUNG
  • Publication number: 20240047856
    Abstract: An electronic device includes a metal back cover, a metal frame, and two radiators. The metal frame disposed at a side of the metal back cover includes two disconnecting parts, a second slot, and two connecting parts. A first slot is formed between each of the disconnecting parts and the metal back cover. The second slot is formed between the two disconnecting parts. The two connecting parts are connected to a side away from the second slot of the two disconnecting parts respectively and are connected to the metal back cover. Each of the radiators connects the metal back cover to the corresponding disconnecting part over the first slot. The two radiators are disposed symmetrically based on the second slot. Each radiator is coupled with the corresponding disconnecting part, the corresponding connecting part, and the metal back cover to resonate a first, a second, and a third frequency band.
    Type: Application
    Filed: July 19, 2023
    Publication date: February 8, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Shih-Keng Huang, Hau Yuen Tan, Cheng-Hsiung Wu, Sheng-Chin Hsu, Tse-Hsuan Wang
  • Patent number: 11894312
    Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
  • Patent number: 11894318
    Abstract: A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11895199
    Abstract: Updating a user social network profile of a user based on relevant activities posted by other users in a same social network.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: February 6, 2024
    Assignee: KYNDRYL, INC.
    Inventors: Yan Bin Fu, Qing Jun Gao, Shuang Yin Liu, Wen Wang, Yi Wu