Patents by Inventor Yi Wu
Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250226137Abstract: A magnetic positioning structure for an expanded device includes a magnetic positioning plate and at least one magnetic conductive element. The magnetic positioning plate with a fixing surface and a mounting surface fixed on a plane includes at least one first magnetic element and an anti-slip sleeve, the first magnetic element is enclosed in the anti-slip sleeve, and the magnetic conductive element is arranged in a housing of the expanded device. In this way, the magnetic conductive element can quickly and temporarily fix the expanded device to the mounting surface of the magnetic positioning plate, and the anti-slip sleeve can prevent displacement of the expanded device. The magnetic positioning structure is applicable to expanded devices such as hubs, notebook docking stations, power banks, etc. to prevent random shaking, keep the operating environment neat without causing wire entanglement or affecting connection angles, thus greatly improving the convenience of use.Type: ApplicationFiled: August 30, 2024Publication date: July 10, 2025Inventors: CHUNG-YING CHANG, HUNG-YI LIN, ZHENG-YI WU
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Publication number: 20250224637Abstract: An optical film comprises a substrate and a plurality of microstructures positioned on a light incident surface of the substrate. The substrate is defined to have a first direction and a second direction perpendicular to the first direction. The cross-sectional shape of the microstructures in the first direction is different from that in the second direction. Each of the microstructures has multiple optical surfaces and a boundary line connecting the multiple optical surfaces. The boundary line is a straight line and parallel to the light incident surface of the substrate. Through the structural design of the microstructures on the optical film, the light distribution of the light source is expanded to achieve the purpose of specific angle illumination. The present invention also provides a backlight module and a display device including the optical film.Type: ApplicationFiled: March 28, 2025Publication date: July 10, 2025Applicant: Radiant Opto-Electronics CorporationInventors: Chun-Yi WU, Wei-Hsuan CHEN, Yung-Hui TAI, Chung-Yung TAI, Wen-Hao CAI, Chun-Hau LAI, Jun-Ping LIN
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Patent number: 12355165Abstract: An electronic device including a metal bottom plate, a metal frame and at least one radiator is provided. The metal bottom plate includes at least one ground terminal. The metal frame includes at least one slot, at least one disconnecting part, at least one first connecting part and at least one second connecting part. The disconnecting part includes a first part and a second part. Each radiator includes a first terminal and a second terminal. The second terminal is connected to a junction between the first part and the second part. The first terminal, the second terminal, the first part, the first connecting part and the ground terminal form a first antenna path radiating at a first frequency band. The first terminal, the second terminal, the second part, the second connecting part and the ground terminal form a second antenna path radiating at a second frequency band.Type: GrantFiled: May 15, 2023Date of Patent: July 8, 2025Assignee: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Chih-Wei Liao, Chao-Hsu Wu, Hau Yuen Tan, Shih-Keng Huang, Cheng-Hsiung Wu, Chia-Hung Chen, Sheng-Chin Hsu, Hao-Hsiang Yang
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Patent number: 12354924Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.Type: GrantFiled: April 10, 2024Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
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Patent number: 12356558Abstract: An electronic assembly includes a first wafer including a stack of alternating first dielectric layers and first circuit layers, a flexible structure including a second dielectric layer and a second circuit layer covered by the second dielectric layer, and a second wafer stacked upon the first wafer and including chip packages arranged in an array. The flexible structure includes a first region embedded in the first wafer and a second region connected to the first region and extending out from an edge of the first wafer. The chip packages are electrically coupled to the second circuit layer of the flexible structure through the first circuit layers of the first wafer.Type: GrantFiled: April 18, 2023Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
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Patent number: 12354969Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.Type: GrantFiled: November 28, 2023Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien-Hsun Lee
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Publication number: 20250216445Abstract: A chip cooling module and a chip testing apparatus having the same are provided. The chip cooling module includes a socket and a fluid supply device. The socket includes a chip slot and at least one fluid channel, and the chip slot is configured to accommodate a chip. The fluid supply device is in communication with the at least one fluid channel of the socket. The at least one fluid channel includes a divergent opening, and the divergent opening is provided on a sidewall of the socket and faces the chip slot. In response to the fluid supply device supplying a cooling fluid to the at least one fluid channel, the cooling fluid forms a jet stream toward the chip slot through the divergent opening.Type: ApplicationFiled: November 22, 2024Publication date: July 3, 2025Applicant: CHROMA ATE INC.Inventors: Yu-Wei Chuang, Xin-Yi Wu, Jui-Che Chou
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Publication number: 20250216444Abstract: An anti-condensation low-temperature testing module and a chip testing apparatus having the same are provided. The low-temperature testing module includes a low-temperature dry-gas supplying device, a low-temperature chamber, a low-temperature generating device, and a communicating pipe. The low-temperature dry-gas supplying device is configured to provide a low-temperature dry-gas to a chip socket of a testing base. The low-temperature generating device is arranged in the low-temperature chamber and coupled to the testing base. The low-temperature generating device is configured to cool down the testing base. One of two ends of the communicating pipe is in communication with the chip socket of the testing base, and the other end of the communicating pipe is in communication with the low-temperature chamber.Type: ApplicationFiled: September 11, 2024Publication date: July 3, 2025Applicant: CHROMA ATE INC.Inventors: Yu-Wei Chuang, Xin-Yi Wu, Jui-Che Chou
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Publication number: 20250212893Abstract: Present invention teaches the method of using a keratin hydrolyzed peptide (“KHP”) solution to improve the growth of cotton under low temperature conditions. By selectively choosing specific weights of feathers and water, and treating the mixture to a high-temperature high-pressure hydrolysis process, the resulting solution is confirmed to contain at least 253 peptides and then infused to the soil containing the cotton seeds, the solution can also be sprayed to the leaf surface of cotton plants at a specific growth stage. Optionally, the KHP solution can be diluted by water, as disclosed in the specification, for applying to the soil and for spraying to leaf surface of cotton seedlings/plants.Type: ApplicationFiled: June 28, 2024Publication date: July 3, 2025Applicant: CH Biotech R&D Co., Ltd.Inventors: Jenn Wen HUANG, Yi-Chiao CHAN, Yu-Yi WU, Nai-Hua YE
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Publication number: 20250219809Abstract: An encryption and decryption device includes a ShiftRow/InvShiftRow unit, a SubBytes/InvSubBytes unit, a dual ShiftRow/InvShiftRow unit, an encoder, a decoder, and a first verification unit. The ShiftRow/InvShiftRow unit performs a row shift/inverse row shift operation on result data to generate an input state array. The subbytes/invsubbytes unit performs a transformation on the input state array to generate an output state array. The dual ShiftRow/InvShiftRow unit performs the row shift/inverse row shift operation on dual output data to generate a dual input state array. The encoder encodes the dual input state to generate encoded data. The decoder decodes the encoded data to generate decoded data. The first verification unit verifies the mapping relationship of the decoded data and the output state array to generate a first verification signal.Type: ApplicationFiled: December 20, 2024Publication date: July 3, 2025Inventors: Kun-Yi WU, Yu-Shan LI
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Patent number: 12347038Abstract: In various example embodiments, techniques are provided for crack detection, assessment and visualization that utilize deep learning in combination with a 3D mesh model. Deep learning is applied to a set of 2D images of infrastructure to identify and segment surface cracks. For example, a Faster region-based convolutional neural network (Faster-RCNN) may identify surface cracks and a structured random forest edge detection (SFRED) technique may segment the identified surface cracks. Alternatively, a Mask region-based convolutional neural network (Mask-RCNN) may identify and segment surface cracks in parallel. Photogrammetry is used to generate a textured three-dimensional (3D) mesh model of the infrastructure from the 2D images. A texture cover of the 3D mesh model is analyzed to determine quantitative measures of identified surface cracks. The 3D mesh model is displayed to provide a visualization of identified surface cracks and facilitate inspection of the infrastructure.Type: GrantFiled: September 22, 2020Date of Patent: July 1, 2025Assignee: Bentley Systems, IncorporatedInventors: Zheng Yi Wu, Rony Kalfarisi, Ken Soh
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Patent number: 12347802Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.Type: GrantFiled: August 9, 2023Date of Patent: July 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei-Yu Chen, Chi-Yang Yu, Kuan-Lin Ho, Chin-Liang Chen, Yu-Min Liang, Jiun Yi Wu
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Publication number: 20250205038Abstract: A tissue scaffold is provided. The tissue scaffold includes a textile formed by interweaving a plurality of warp yarns and a plurality of weft yarns. The textile includes a first region and a second region, and the second region is adjacent to the first region. The plurality of warp yarns have different diameters in the first region and the second region. The textile has a plurality of pores, and the size of each of the plurality of pores is between 100 ?m and 800 ?m. A method of manufacturing the aforementioned tissue scaffold is also provided.Type: ApplicationFiled: December 27, 2023Publication date: June 26, 2025Applicant: Industrial Technology Research InstituteInventors: Chih-Chieh Huang, Lih-Tao HSU, Cheng-Yi WU, Meng-Hsueh LIN, Hui-Ting HUANG, Chen-Hsuan LIN, Yi-Hung WEN, Fang-Chieh CHANG, Hsin-Hsin SHEN, Pei-I TSAI, Jun-Jae HUANG
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Patent number: 12342436Abstract: A light strip unplugging protection method includes: providing a light strip, wherein the light strip includes a plug including a power pin and a control pin; providing a socket corresponding to the plug, wherein the socket includes a power pin holder and at least one light strip control pin holder for electrically connecting with the power pin and the light strip control pin respectively; using a pulse-width modulation signal to drive the light strip on the light strip control pin holder to control the current passing therethrough; and when the pulse-width modulation signal is in a first state, detecting voltage or current of the light strip control pin holder; determining whether the light strip is unplugged according to the voltage or current; and when it is determined that the light strip is unplugged, power voltage on the power pin holder is turned off.Type: GrantFiled: September 22, 2023Date of Patent: June 24, 2025Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Lian-Cheng Tsai, Chun-Yi Wu
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Publication number: 20250200136Abstract: An encryption/decryption device includes a SubBytes/InvSubBytes unit, a MixColumns/InvMixColumns unit, a first verification unit, and a controller. The SubBytes/InvSubBytes unit performs a transformation on the input state array to generate an output state array. The MixColumns/InvMixColumns unit performs a mix column operation/inverse mix column operation on the output state array to generate a mix-column/inverse mix-column array. The mix column operation/inverse mix column operation includes a binary-field multiplication calculation. The first verification unit determines whether the output state array and the mix-column/inverse mix-column array meet a mapping relationship to generate a verification signal. The controller determines whether the binary field multiplication calculation performed by the MixColumns/InvMixColumns unit is correct based on the first verification signal.Type: ApplicationFiled: December 3, 2024Publication date: June 19, 2025Inventors: Kun-Yi WU, Yu-Shan LI
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Publication number: 20250201528Abstract: Methods for revitalizing components of a plasma processing apparatus that includes a sensor for detecting a thickness or roughness of a peeling weakness layer on a protective surface coating of a plasma processing tool and/or for detecting airborne contaminants generated by such peeling weakness layer. The method includes detecting detrimental amounts of peeling weakness layer buildup or airborne concentration of atoms or molecules from the peeling weakness layer, and initiating a revitalization process that bead beats the peeling weakness layer to remove it from the component while maintaining the integrity of the protective surface coating.Type: ApplicationFiled: February 26, 2025Publication date: June 19, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Hsing LIN, Chen-Fon CHANG, Chun-Yi WU, Shi Yu KE, Chih-Teng LIAO
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Patent number: 12334362Abstract: A method of forming a semiconductor package includes: bonding a first wafer to a second wafer, where the first wafer includes a plurality of electronic dies, and the second wafer includes a plurality of photonic dies; after bonding the first wafer, forming trenches in the second wafer between adjacent ones of the plurality of photonic dies; filling the trenches with an optical glue; and dicing the first wafer and the second wafer to form a plurality of photonic packages, where a photonic package of the plurality of photonic packages includes an electronic die, a photonic die bonded to the electronic die, and the optical glue, where the optical glue extends along a sidewall of the photonic package.Type: GrantFiled: January 5, 2023Date of Patent: June 17, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiun Yi Wu, Chen-Hua Yu
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Patent number: 12334446Abstract: A semiconductor structure includes a first redistribution structure, a first local interconnect component disposed on the first redistribution structure, and a first interconnect structure over a second side of the first local interconnect component. The first local interconnect component includes a first plurality of redistribution layers. The first plurality of redistribution layers includes a first plurality of conductive features on a first side of the first local interconnect component. Each of the first plurality of conductive features are coupled to respective conductive features of the first redistribution structure. The first interconnect structure includes a second plurality of conductive features and a third plurality of conductive features. The second plurality of conductive features are electrically coupled to the third plurality of conductive features through the first local interconnect component.Type: GrantFiled: June 17, 2024Date of Patent: June 17, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
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Patent number: 12332472Abstract: An optical film comprises a light incident side and a light emitting side opposite to the light incident side. A plurality of light incident microstructures are formed on the light incident side, and the light incident microstructures are tapered structures. According to the structural design of the light incident microstructures of the optical film, the light field of a light source can be expanded to achieve the purpose of emitting light at a specific angle. The invention also provides a backlight module and a display device including the optical film.Type: GrantFiled: September 5, 2023Date of Patent: June 17, 2025Assignee: Radiant Opto-Electronics CorporationInventors: Wei-Hsuan Chen, Chung-Yung Tai, Wen-Hao Cai, Chun-Yi Wu
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Patent number: 12334287Abstract: The present disclosure discloses a vacuum degree detection device, a monitoring system and a vacuum arc-extinguishing chamber thereof, wherein, in the vacuum degree detection device, a ceramic insulating housing is sealingly fixed to an end face cover plate of the vacuum arc-extinguishing chamber, the ceramic insulating housing is a circular ring-shaped structure coaxial with a conductive rod on the end face cover plate, a sealing area formed by the end face cover plate and the ceramic insulating housing is provided with a through hole communicating with the vacuum arc-extinguishing chamber; a thermoelectric vacuum sensor is disposed inside the ceramic insulating housing to detect the vacuum degree of the vacuum arc-extinguishing chamber, a cold end is fixed to the end face cover plate, an electrode is supported on the cold end, a thermoelectric arm is supported on the electrode, a hot end is laminated to the thermoelectric arm.Type: GrantFiled: May 22, 2023Date of Patent: June 17, 2025Assignee: XI'AN JIAOTONG UNIVERSITYInventors: Yi Wu, Hailong He, Chunping Niu, Mingzhe Rong, Hongrui Ren, Xiaolong Chen