Patents by Inventor Yi-Yang Lei
Yi-Yang Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
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Publication number: 20240063048Abstract: A workpiece chuck includes a supporting platform, a vacuum system, and a gas permeable buffer layer. The supporting platform has a supporting surface for holding a workpiece thereon. The vacuum system is disposed under and in gas communication with the supporting platform. The gas permeable buffer layer is disposed over the supporting platform and covers the supporting surface, wherein a hardness scale of the gas permeable buffer layer is smaller than a hardness scale of the supporting platform.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ching Lo, Ching-Pin Yuan, Wei-Jie Huang, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
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Patent number: 11878388Abstract: A polishing pad, a polishing apparatus and a method of manufacturing a semiconductor package using the same are provided. In some embodiments, a polishing pad includes a sub-pad portion and a top pad portion over the sub-pad portion. The top pad portion includes a plurality of grooves having a first width and a plurality of openings having a second width different from the first width, and the openings are located in a center zone of the polishing pad.Type: GrantFiled: June 15, 2018Date of Patent: January 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Cheng Wang, Ching-Hua Hsieh, Yi-Yang Lei
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Publication number: 20240017538Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.Type: ApplicationFiled: August 2, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Jie Huang, Yu-Ching Lo, Ching-Pin Yuan, Wen-Chih Lin, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
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Publication number: 20230352442Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20230307404Abstract: A package structure includes a die, a first redistribution circuit structure, a first redistribution circuit structure, a second redistribution circuit structure, an enhancement layer, first conductive terminals, and second conductive terminals. The first redistribution circuit structure is disposed on a rear side of the die and electrically coupled to thereto. The second redistribution circuit structure is disposed on an active side of the die and electrically coupled thereto. The enhancement layer is disposed on the first redistribution circuit structure. The first redistribution circuit structure is disposed between the enhancement layer and the die. The first conductive terminals are connected to the first redistribution circuit structure. The first redistribution circuit structure is between the first conductive terminals and the die. The second conductive terminals are connected to the second redistribution circuit structure.Type: ApplicationFiled: March 28, 2022Publication date: September 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Yu-Ching Lo, Wei-Jie Huang, Ching-Pin Yuan, Yi-Che Chiang, Kris Lipu Chuang, Hsin-Yu Pan, Yi-Yang Lei, Ching-Hua Hsieh, Kuei-Wei Huang
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Patent number: 11742317Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: GrantFiled: October 17, 2019Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20230115449Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
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Patent number: 11587902Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: GrantFiled: September 19, 2019Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Patent number: 11569183Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.Type: GrantFiled: December 14, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
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Publication number: 20220314595Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.Type: ApplicationFiled: August 5, 2021Publication date: October 6, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Jie Huang, Yu-Ching Lo, Ching-Pin Yuan, Wen-Chih Lin, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
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Publication number: 20220262758Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.Type: ApplicationFiled: May 9, 2022Publication date: August 18, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
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Patent number: 11355466Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.Type: GrantFiled: June 10, 2020Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
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Patent number: 11270921Abstract: A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.Type: GrantFiled: May 8, 2020Date of Patent: March 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Cheng Hou, Chien-Hsun Lee, Chung-Shi Liu, Jung-Wei Cheng, Tsung-Ding Wang, Yi-Yang Lei
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Publication number: 20210242100Abstract: A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.Type: ApplicationFiled: May 8, 2020Publication date: August 5, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-Cheng Hou, Chien-Hsun Lee, Chung-Shi Liu, Jung-Wei Cheng, Tsung-Ding Wang, Yi-Yang Lei
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Publication number: 20210242159Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.Type: ApplicationFiled: June 10, 2020Publication date: August 5, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
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Patent number: 11069652Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.Type: GrantFiled: January 14, 2020Date of Patent: July 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
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Publication number: 20210098395Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
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Patent number: 10867939Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.Type: GrantFiled: June 14, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
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Patent number: 10790252Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.Type: GrantFiled: July 31, 2018Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yi-Yang Lei, Szu-Yu Yeh, Yu-Ren Chen, Hung-Jui Kuo, Chung-Shi Liu