Patents by Inventor Yi-Yang Lei

Yi-Yang Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming semiconductor die
    Patent number: 8258055
    Abstract: An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Zheng-Yi Lim, Yi-Yang Lei, Cheng-Chung Lin, Chung-Shi Liu
  • Method for Reducing UBM Undercut in Metal Bump Structures
    Publication number: 20120064712
    Abstract: A method of forming a device includes providing a wafer including a substrate; and forming an under-bump metallurgy (UBM) layer including a barrier layer overlying the substrate and a seed layer overlying the barrier layer. A metal bump is formed directly over a first portion of the UBM layer, wherein a second portion of the UBM layer is not covered by the metal bump. The second portion of the UBM layer includes a seed layer portion and a barrier layer portion. A first etch is performed to remove the seed layer portion, followed by a first rinse step performed on the wafer. A second etch is performed to remove the barrier layer portion, followed by a second rinse step performed on the wafer. At least a first switch time from the first etch to the first rinse step and a second switch time from the second etch to the second rinse step is less than about 1 second.
    Type: Application
    Filed: September 14, 2010
    Publication date: March 15, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Yang Lei, Hung-Jui Kuo, Chung-Shi Liu
  • CONDUCTIVE BUMP FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE
    Publication number: 20120007230
    Abstract: An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Zheng-Yi Lim, Yi-Yang Lei, Cheng-Chung Lin, Chung-Shi Liu