Patents by Inventor Yi Yi

Yi Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250115551
    Abstract: The present invention relates to Ras inhibitors, intermediates in the synthesis thereto, and methods for preparing the Ras inhibitors and the intermediates.
    Type: Application
    Filed: October 2, 2024
    Publication date: April 10, 2025
    Inventors: Yi LI, Benjamin MENDOZA, Sriram NAGANATHAN, Ross WANG, Yi YI, Steven G. BALLMER, James DAVIDSON, Xiaojun HUANG
  • Publication number: 20250089364
    Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Inventors: Cheng-Ling WU, Chih-Liang CHEN, Chi-Yu LU, Yi-Yi CHEN, Ting-Yun WU
  • Publication number: 20250038070
    Abstract: A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Inventors: Yi-Yi Chen, Chi-Yu Lu, Chih-Liang Chen, LI-CHUN TIEN
  • Publication number: 20240429167
    Abstract: An integrated circuit includes a first-type active-region structure and a second-type active-region structure extending in a first direction and a first terminal-conductor and a second terminal-conductor extending in a second direction. The integrated circuit also includes a first power stub and a second power stub in a first metal layer and a first power line and a second power line in a second metal layer. The integrated circuit further includes a first via connector directly connected between the first power stub and the first terminal-conductor, a second via connector directly connected between the second power stub and the second terminal-conductor, a third via connector directly connected between the first power stub and the first power line, and a fourth via connector directly connected between the second power stub and the second power line.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Inventors: Yi-Yi CHEN, Li-Chun TIEN, Chih-Liang CHEN, Wei-Cheng LIN, Jiann-Tyng TZENG, Chi-Yu LU
  • Publication number: 20240385187
    Abstract: This disclosure relates to bifunctional Janus reporter particles to simultaneously monitor two or more functions within a single cell. such as simultaneously monitoring acidification and proteolysis in a single phagosome in live cells. Exemplary Janus reporter particles include a pH reporter and a proteolysis reporter that are spatially separated but function concurrently.
    Type: Application
    Filed: September 16, 2022
    Publication date: November 21, 2024
    Inventors: Yi Yi, Yan Yu, Seonik Lee
  • Publication number: 20240371949
    Abstract: A semiconductor structure includes a first upper source/drain region, a second upper source/drain region, a first lower source/drain contact, a second lower source/drain contact, and a third conductive region. The first upper source/drain contact is disposed at a first elevation. The second upper source/drain contact is disposed at the first elevation. The first lower source/drain contact is disposed at a second elevation. The second lower source/drain contact is disposed at the second elevation. The third conductive region is disposed at a third elevation. A projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact. The third elevation is disposed between the first elevation and the second elevation.
    Type: Application
    Filed: May 7, 2023
    Publication date: November 7, 2024
    Inventors: YI-YI CHEN, CHI-YU LU, CHIH-LIANG CHEN
  • Patent number: 12125435
    Abstract: The present disclosure provides a pixel circuit with pulse width compensation, and the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, and the pulse amplitude modulation circuit is electrically connected to the pulse width modulation circuit. The pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, and the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor. The pulse amplitude modulation circuit includes a second P-type control transistor, a first capacitor, a P-type driving transistor and a light-emitting element. The second P-type control transistor is electrically connected to the first P-type control transistor. The first capacitor is electrically connected to the second P-type control transistor.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: October 22, 2024
    Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (ShenZhen) Co., Ltd., General Interface Solution Limited
    Inventors: De-Fu Chen, Po Lun Chen, Chun-Ta Chen, Ta-Jen Huang, Po-Tsun Liu, Guang-Ting Zheng, Ting-Yi Yi
  • Publication number: 20240329171
    Abstract: A magnetic field enhancing component, including: a first dielectric layer comprising a first surface and a second surface opposite to each other; a first electrode layer arranged on the first surface; a second electrode layer and a fourth electrode layer, which are arranged on the second surface at an interval, where orthographic projections of the first electrode layer and the second electrode layer, which are projected onto the first dielectric layer, overlap each other, and orthographic projections of the first electrode layer and the fourth electrode layer, which are projected onto the first dielectric layer, overlap each other; and a first external capacitor, a second external capacitor, and a first switching control circuit. One terminal of the second external capacitor is connected to the second electrode layer, and another terminal of the second external capacitor is connected to one terminal of the first external capacitor and one terminal of the first switching control circuit, respectively.
    Type: Application
    Filed: August 9, 2021
    Publication date: October 3, 2024
    Inventors: QIAN ZHAO, ZHONG-HAI CHI, YONG-GANG MENG, ZHUO-ZHAO ZHENG, YI YI, YA-KUI WANG
  • Publication number: 20240233674
    Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.
    Type: Application
    Filed: December 11, 2022
    Publication date: July 11, 2024
    Inventors: De-Fu CHEN, Po Lun CHEN, Chun-Ta CHEN, Ta-Jen HUANG, Po-Tsun LIU, Guang-Ting ZHENG, Ting-Yi YI
  • Publication number: 20240144868
    Abstract: The present disclosure provides a pixel circuit with pulse width compensation, and the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, and the pulse amplitude modulation circuit is electrically connected to the pulse width modulation circuit. The pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, and the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor. The pulse amplitude modulation circuit includes a second P-type control transistor, a first capacitor, a P-type driving transistor and a light-emitting element. The second P-type control transistor is electrically connected to the first P-type control transistor. The first capacitor is electrically connected to the second P-type control transistor.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Inventors: De-Fu CHEN, Po Lun CHEN, Chun-Ta CHEN, Ta-Jen HUANG, Po-Tsun LIU, Guang-Ting ZHENG, Ting-Yi YI
  • Publication number: 20240135897
    Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.
    Type: Application
    Filed: December 11, 2022
    Publication date: April 25, 2024
    Inventors: De-Fu CHEN, Po Lun CHEN, Chun-Ta CHEN, Ta-Jen HUANG, Po-Tsun LIU, Guang-Ting ZHENG, Ting-Yi YI
  • Patent number: 11961489
    Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.
    Type: Grant
    Filed: December 11, 2022
    Date of Patent: April 16, 2024
    Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (ShenZhen) Co., Ltd., General Interface Solution Limited
    Inventors: De-Fu Chen, Po Lun Chen, Chun-Ta Chen, Ta-Jen Huang, Po-Tsun Liu, Guang-Ting Zheng, Ting-Yi Yi
  • Patent number: 11942425
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a contact structure, a first conductive element, and a first dielectric spacer structure. The semiconductor substrate includes an active region and an isolation structure. The contact structure is on the active region of the semiconductor substrate. The first conductive element is on the isolation structure of the semiconductor substrate. The first dielectric spacer structure is between the contact structure and the first to conductive element. The first dielectric spacer structure has a first concave surface facing the first conductive element.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 26, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Ying Tsai, Jui-Seng Wang, Yi-Yi Chen
  • Patent number: 11903179
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a semiconductor substrate including an active region and an isolation structure. The method also includes forming a contact structure on the active region of the semiconductor substrate. The method further includes forming a dielectric spacer on opposite sides of the contact structure. The method also includes forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: February 13, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Ying Tsai, Jui-Seng Wang, Yi-Yi Chen
  • Publication number: 20240008266
    Abstract: The present application provides a method of fabricating bit line contacts. The method includes steps of depositing an insulative layer and a sacrificial layer on the substrate; forming a photosensitive layer on the sacrificial layer; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to form an intermediate pattern on the sacrificial layer; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to form a target pattern on the sacrificial layer; performing a first etching process to remove portions of the sacrificial layer exposed by the target pattern; performing a second etching process to form a plurality of trenches in the insulative layer; and depositing a conductive material into the plurality of trenches to form the bit line contacts.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Inventors: CHIH-YING TSAI, JUI-SENG WANG, YI-YI CHEN
  • Publication number: 20240004300
    Abstract: The present application provides a method of processing a substrate. The method of processing the substrate includes steps of forming a photosensitive layer on the substrate; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to remove portions of the photosensitive layer exposed to the actinic radiation and form an intermediate pattern; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to remove portions of the intermediate pattern shielded from the actinic radiation and form a target pattern; and performing an etching process to remove portions of the substrate exposed by the target pattern.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Inventors: CHIH-YING TSAI, JUI-SENG WANG, YI-YI CHEN
  • Publication number: 20230335490
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a contact structure, a first conductive element, and a first dielectric spacer structure. The semiconductor substrate includes an active region and an isolation structure. The contact structure is on the active region of the semiconductor substrate. The first conductive element is on the isolation structure of the semiconductor substrate. The first dielectric spacer structure is between the contact structure and the first to conductive element. The first dielectric spacer structure has a first concave surface facing the first conductive element.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: CHIH-YING TSAI, JUI-SENG WANG, YI-YI CHEN
  • Publication number: 20230337411
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a semiconductor substrate including an active region and an isolation structure. The method also includes forming a contact structure on the active region of the semiconductor substrate. The method further includes forming a dielectric spacer on opposite sides of the contact structure. The method also includes forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: CHIH-YING TSAI, JUI-SENG WANG, YI-YI CHEN
  • Publication number: 20230263455
    Abstract: Provided here are non-invasive methods for evaluating functional connectivity patterns in localized brain regions of a patient involving application of a MS-specific functional meta-analytic connectivity model in resting-state functional magnetic resonance imaging (rsfMRI) data to provide patients with appropriate medical care in response to output from the model.
    Type: Application
    Filed: May 29, 2021
    Publication date: August 24, 2023
    Inventors: Florence Yi Yi Ling CHIANG, Peter T. FOX, Rebecca S. Romero, Larry PRICE
  • Patent number: 11655509
    Abstract: Disclosed herein is a kit for diagnosing spinal muscular atrophy (SMA) in a human subject based on the copy numbers of exons 7 and 8 of SMN1 gene and the copy numbers of exons 7 and 8 of SMN2 gene in a DNA sample isolated from the human subject. Also disclosed herein are methods of diagnosing SMA by use of the present kit, and methods of treating SMA based on the diagnostic result.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: May 23, 2023
    Assignee: Origin Biotechnology Co., Ltd.
    Inventors: Yi-Yi Kuo, I-Fan Chiu, Lai-Ha Chung, Shu-Ju Lee