Patents by Inventor Yi Yu

Yi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11661131
    Abstract: A headlight horizontal lighting pattern adjustment system includes an inclination angle sensor connected to a vehicle to sense an inclination angle value of the vehicle. A processing unit receives the inclination angle value and processes the inclination angle value into a driving value. A driving module drives a lighting device. The driving module commands the driving device to driving and rotate the lighting device according the driving value. The headlight horizontal lighting pattern adjustment system is equipped to a motorbike or an electric motorbike. When the motorbike turns and tilt, the processing unit adjusts the light of the lighting device by the driving module and the driving device to eliminate dark corners in the dark zone and maintains the full scale of light pattern to enhance safety to all the road users.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: May 30, 2023
    Assignee: Ta Yih Industrial Co., Ltd.
    Inventor: Cheng-Yi Yu
  • Patent number: 11652058
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Kuei-Ming Chen
  • Publication number: 20230140953
    Abstract: The invention provides compositions comprising novel programmable adenosine base editor systems (e.g., ABE8) that provide methods of treating a disease or disorder, (e.g., Parkinson's disease, Hurler syndrome, Rett syndrome, or Stargardt disease) in a subject by administering to the subject a programmable adenosine base editor system (e.g., ABE8) that have increased efficiency and methods of using these adenosine deaminase variants for editing a disease-associated gene.
    Type: Application
    Filed: February 13, 2020
    Publication date: May 11, 2023
    Applicant: BEAM THERAPEUTICS INC.
    Inventors: Ian SLAYMAKER, Nicole GAUDELLI, Yi YU, Bernd ZETSCHE, David A. BORN, Seung-Joo LEE, Michael PACKER, Jason Michael GEHRKE, Natalie PETROSSIAN, Angelica MESSANA, Shaunna BERKOVITCH
  • Publication number: 20230136441
    Abstract: A resistive random access memory (RRAM) structure includes a substrate. A transistor is disposed on the substrate. The transistor includes a gate structure, a source and a drain. A drain contact plug contacts the drain. A metal interlayer dielectric layer is disposed on the drain contact plug. An RRAM is disposed on the drain and within a first trench in the metal interlayer dielectric layer. The RRAM includes the drain contact plug, a metal oxide layer and a top electrode. The drain contact plug serves as a bottom electrode of the RRAM. The metal oxide layer contacts the drain contact plug. The top electrode contacts the metal oxide layer and a metal layer is disposed within the first trench.
    Type: Application
    Filed: December 2, 2021
    Publication date: May 4, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Yu Lin, Po-Kai Hsu, Chung-Yi Chiu
  • Publication number: 20230135098
    Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.
    Type: Application
    Filed: December 3, 2021
    Publication date: May 4, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Yi Yu Lin, Po Kai Hsu, Chun-Hao Wang, Yu-Ru Yang, Ju Chun Fan, Chung Yi Chiu
  • Publication number: 20230128472
    Abstract: The present invention features compositions and methods for editing deleterious mutations associated with hemoglobinopathies, such as sickle cell disease (SCD). In particular embodiments, the invention provides methods for correcting mutations in a beta globin polynucleotide using modified adenosine base editors termed “ABE8” having unprecedented levels (e.g., >60-70%) of efficiency.
    Type: Application
    Filed: July 26, 2022
    Publication date: April 27, 2023
    Applicant: Beam Therapeutics Inc.
    Inventors: Ian SLAYMAKER, Nicole GAUDELLI, Yi YU, Bernd ZETSCHE, David A. BORN, Seung-Joo LEE, Michael PACKER
  • Publication number: 20230130248
    Abstract: A system and method are disclosed for providing uplink timing synchronization during DRX operation in a wireless communication system.
    Type: Application
    Filed: December 22, 2022
    Publication date: April 27, 2023
    Inventors: James Earl WOMACK, Yi YU, Zhijun CAI
  • Publication number: 20230131830
    Abstract: Pyrimidine compounds of Formula (I). Assignments to the variables in the formula are set forth herein. Also disclosed is a method of treating cancer with one of the pyrimidine compounds.
    Type: Application
    Filed: March 3, 2021
    Publication date: April 27, 2023
    Inventors: Chun-Ping Chang, Ya-Hui Chi, Chiung-Tong Chen, Chuan Shih, Yi-Yu Ke
  • Patent number: 11637233
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Grant
    Filed: November 1, 2020
    Date of Patent: April 25, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Patent number: 11630903
    Abstract: In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 18, 2023
    Assignee: Apple Inc.
    Inventors: Timothy R. Paaske, Mitchell D. Adler, Conrad Sauerwald, Fabrice L. Gautier, Shu-Yi Yu
  • Patent number: 11626693
    Abstract: An electrical connector includes a body and multiple conductive terminals. The body has an insertion slot. Each conductive terminal has a contact portion entering the insertion slot and a conductive portion passing downward beyond a bottom surface of the body. Each side of the insertion slot has first terminal groups and second terminal groups. The conductive portions of each first terminal group are located away from the insertion slot relative to the conductive portions of each second terminal group. The conductive portions are provided in four rows in a lateral direction. The conductive terminals include signal terminals and ground terminals. The circuit board has an adjusting hole and four rows of connecting points corresponding to the conductive portions. Each row of the connecting points include multiple signal connecting points and multiple ground connecting points. The adjusting hole is located between two signal connecting points in two adjacent rows.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: April 11, 2023
    Assignee: LOTES CO., LTD
    Inventors: Xin Hu, Yi Yu, Zhi Jie Li
  • Patent number: 11627561
    Abstract: A method for informing a relay node when to receive data. The method includes the relay node being informed of a fixed point in a subframe of data when an access node will begin transmitting relevant data over a physical downlink shared channel. The method further includes the relay node beginning to receive data at approximately the fixed point.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: April 11, 2023
    Assignee: BlackBerry Limited
    Inventors: Yi Yu, Zhijun Cai, James Earl Womack
  • Publication number: 20230101597
    Abstract: The present invention features compositions and methods for editing deleterious mutations associated with alpha-1 anti-trypsin (A1AT) deficiency. In particular embodiments, the invention provides methods for correcting mutations in an A1AT polynucleotide using an adenosine deaminase base editor, ABE8, having unprecedented levels of efficiency.
    Type: Application
    Filed: February 13, 2020
    Publication date: March 30, 2023
    Applicant: BEAM THERAPEUTICS INC.
    Inventors: Nicole GAUDELLI, Michael PACKER, Bernd ZETSCHE, Ian SLAYMAKER, Yi YU, David A. BORN, Seung-Joo LEE
  • Publication number: 20230084115
    Abstract: An electrical connector has a test terminal, a positive terminal, and a negative terminal coaxially mounted in a connector base. The negative terminal surrounds the positive terminal. An insulating cap is mounted between the positive terminal and the negative terminal. A pair of turning engaging parts is formed between the ring body of the insulating cap and the internal surface of the negative terminal and the turning engaging parts are engaged with each other to assemble the insulating cap with the negative terminal by turning the insulating cap. An annular groove is formed in a top of the insulating cap to increase a creepage distance between the negative terminal and the positive terminal to meet requirement of safety specifications.
    Type: Application
    Filed: November 18, 2021
    Publication date: March 16, 2023
    Applicant: T-CONN PRECISION CORPORATION
    Inventor: Chien-Yi YU
  • Publication number: 20230080198
    Abstract: The present invention features genetically modified immune cells comprising novel adenosine base editors (e.g., ABE8) having enhanced anti-neoplasia activity, resistance to immune suppression, and decreased risk of eliciting a graft-versus-host reaction or host-versus-graft reaction, or a combination thereof. The present invention also features methods for producing and using these modified immune effector cells.
    Type: Application
    Filed: February 13, 2020
    Publication date: March 16, 2023
    Applicant: BEAM THERAPEUTICS INC.
    Inventors: Nicole GAUDELLI, Michael PACKER, Ian SLAYMAKER, Yi YU, Bernd ZETSCHE, David A. BORN, Seung-Joo LEE, Jason M. GEHRKE
  • Patent number: 11603600
    Abstract: A method of manufacturing a metal mask includes providing a growth substrate with a conductive surface. Then, a cover pattern is formed on the conductive surface, which has at least one opening and an insulated surface touching the conductive surface. Next, using the cover pattern as a mask, a first electroforming is performed to form a mold part on the conductive surface. The mold part fills the opening and has a conductive pattern surface touching the conductive surface. The conductive pattern surface is flush with the insulated surface. After the first electroforming, the growth substrate is removed, while the cover pattern and the mold part are reserved. After removing the growth substrate, a second electroforming is performed to the conductive pattern surface of the mold part to form a metal pattern. Afterwards, the mold part and the cover pattern are removed from the metal pattern.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: March 14, 2023
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventor: Jyun-Yi Yu
  • Publication number: 20230071833
    Abstract: The disclosed technology provides solutions for improving work ticketing triage and in particular, for improving the triage of work orders for detected failure events (or predicted failure events) for a fleet of vehicles, such as a fleet of autonomous vehicles (AVs). In some aspects, a process of the disclosed technology can include steps for receiving field data, processing the field data to identify two or more potential failure events associated with at least one AV from among one or more AVs, and automatically generating a work order for each of the two or more potential failure events. In some aspects, the process can further include steps for calculating a dynamic priority number for each of the two or more potential failure events and sorting the work orders based on the dynamic priority. Systems and machine-readable media are also provided.
    Type: Application
    Filed: September 8, 2021
    Publication date: March 9, 2023
    Inventors: Yi-Yu Chen, Elisha Atkins
  • Patent number: 11602057
    Abstract: A display device including a display panel, a shaft, a correcting sensor and a driving module is provided. The display panel has a display surface. The shaft has an axial end and a correcting end opposite the axial end. The correcting sensor is disposed on the correcting end. When the shaft is rotated relative to the axial end, the correcting sensor is moved to a second position from a first position and faces the display surface at the second position. The driving module is configured to translate the shaft when the correcting sensor is at the second position, such that the correcting sensor can be moved to a detecting position from the second position, wherein the distance of the second position relative to the display surface is greater than the distance of the detecting position relative to the display surface.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 7, 2023
    Assignee: Qisda Corporation
    Inventors: Wu-Shen Lin, Hung-Hsun Liu, Wen-Ching Hsieh, Chin-Yi Yu
  • Publication number: 20230066893
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 2, 2023
    Inventors: Ching-Hung Wang, Yeong-Jyh Lin, Ching I Li, Tzu-Wei Yu, Chung-Yi Yu
  • Publication number: 20230065473
    Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai