Patents by Inventor Yi Yu

Yi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11594606
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Patent number: 11594413
    Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 11594593
    Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Chia-Shiung Tsai, Chung-Yi Yu, Rei-Lin Chu
  • Patent number: 11587325
    Abstract: A method for detecting people entering and leaving a field is provided in an embodiment of the disclosure. The method includes the following. An event detection area corresponding to an entrance is set, and the event detection area includes an upper boundary, a lower boundary, and an internal area, and the lower boundary includes a left boundary, a right boundary, and a bottom boundary; a person image corresponding to a person in an image stream is detected and tracked; and whether the person passes through or does not pass through the entrance is determined according to a first detection result and a second detection result.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: February 21, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Hsin Chang, Yao-Chin Yang, Yi-Yu Su, Kun-Hsien Lu
  • Publication number: 20230050435
    Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
    Type: Application
    Filed: October 26, 2022
    Publication date: February 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
  • Patent number: 11576120
    Abstract: A system and method are disclosed for providing uplink timing synchronization during DRX operation in a wireless communication system.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: February 7, 2023
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: James Earl Womack, Yi Yu, Zhijun Cai
  • Patent number: 11554186
    Abstract: The systems and methods herein involve an infection ultraviolet (UV) device where an enclosed area is exposed to 254 nanometer (nm) radiation, thereby reducing and quarantining airborne pathogens and microbes. This reduces transfer of said pathogens and microbes among individuals equipped with UV protection in the enclosed area.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: January 17, 2023
    Inventor: Yi Yu Lai
  • Patent number: 11551927
    Abstract: A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chung-Chieh Hsu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang, Min-Chang Ching
  • Patent number: 11527702
    Abstract: A device includes a substrate, a first layer of getter material, a first electrode, an insulator element, a second electrode, a first input-output electrode, and a second input-output electrode. The first layer of getter material is deposited on the substrate. The first electrode is formed in a first conductive layer deposited on the first layer of getter material. The first layer of getter material has a getter capacity for hydrogen that is higher than the first electrode. The insulator element is formed in a piezoelectric layer deposited on the first electrode. The second electrode is formed in a second conductive layer deposited on the insulator element. The first input-output electrode is conductively connecting to the first layer of getter material. The second input-output electrode is conductively connecting to the second electrode.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Chung-Yi Yu
  • Patent number: 11522049
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Ming Chen, Chi-Ming Chen, Chung-Yi Yu
  • Patent number: 11522013
    Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: December 6, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
  • Patent number: 11515408
    Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Ming Chen, Chi-Ming Chen, Chung-Yi Yu
  • Publication number: 20220373050
    Abstract: A method and a system for monitoring wear of a braking frictional pad of a motor vehicle, the motor vehicle including a brake device acting on a vehicle wheel, the brake device including a braking frictional pad that is non-rotatable relative to the vehicle wheel and is linearly movable parallel to a rotational axis of the vehicle wheel; a brake piston configured to drive the braking frictional pad; and an electric parking brake or an electric mechanical brake, the electric parking brake or the electric mechanical brake having a drive motor and a piston driving part driven by the drive motor to be linearly movable, the piston driving part being configured to, when the motor vehicle is braking, drive the brake piston to contact the braking frictional pad and in turn drive the braking frictional pad to move.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 24, 2022
    Inventors: Yongxing Jin, Ming Yuan, Yi Yu
  • Publication number: 20220370575
    Abstract: The present invention features compositions and methods for editing deleterious mutations associated with hemoglobinopathies, such as sickle cell disease (SCD). In particular embodiments, the invention provides methods for correcting mutations in a beta globin polynucleotide using modified adenosine base editors termed “ABE8” having unprecedented levels (e.g., >60-70%) of efficiency.
    Type: Application
    Filed: April 13, 2022
    Publication date: November 24, 2022
    Applicant: Beam Therapeutics Inc.
    Inventors: Ian SLAYMAKER, Nicole GAUDELLI, Yi YU, Bernd ZETSCHE, David A. BORN, Seung-Joo LEE, Michael PACKER
  • Publication number: 20220373051
    Abstract: A method and a system for monitoring wear of a braking frictional pad of a motor vehicle, includes stopping the motor vehicle stably on a horizontal or substantially horizontal plane; determining a current fluid level in a brake fluid reservoir; determining a volume difference (?VL) of the brake fluid in the brake fluid reservoir by comparing the determined current fluid level with a predetermined reference fluid level; when a thickness loss of a braking frictional pad equipped for a front vehicle wheel or a rear vehicle wheel is known, determining a thickness loss of a braking frictional pad assigned for the other front vehicle wheel or the other rear vehicle wheel based on the volume difference of the brake fluid in the brake fluid reservoir and a diameter of a brake piston of the respective brake device.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 24, 2022
    Inventors: Yongxing Jin, Ming Yuan, Yi Yu
  • Publication number: 20220367699
    Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).
    Type: Application
    Filed: July 19, 2022
    Publication date: November 17, 2022
    Inventors: Kuei-Ming Chen, Chi-Ming Chen, Chung-Yi Yu
  • Publication number: 20220362460
    Abstract: An infusion apparatus includes a fixture body, a tube socket and a buckling device. The fixture body has a first and a second ends along a first direction. The fixture body has a through hole. Two first protruding pieces are located at the second end along a second direction perpendicular with the first direction. The fixture body penetrates through and is slidable relative with the tube socket which has two grooves along the second direction. The buckling device includes a machine body and two hooking structures. The machine body has a mounting hole. The hooking structures are disposed at opposite sides of the mounting hole and respectively include a hook and a second protruding piece. The hooks buckle within the grooves. A shortest distance between the second protruding pieces is less than a longest distance between the first protruding pieces.
    Type: Application
    Filed: June 14, 2019
    Publication date: November 17, 2022
    Inventors: Shou-tien YIN, Hon-wing AU, Wei-cheng LIN, Chi-lin LEE, Yi-yu LEE
  • Publication number: 20220367791
    Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
    Type: Application
    Filed: June 16, 2021
    Publication date: November 17, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
  • Publication number: 20220367631
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 17, 2022
    Inventors: Kuei-Ming Chen, Chi-Ming Chen, Chung-Yi Yu
  • Publication number: 20220365894
    Abstract: The methods and systems may provide a scalable round-robin arbiter tree that performs round-robin arbitration for a plurality of requests received from a set of requestors. The round-robin arbiter may stack a plurality of round-robin cells in stages where an output of a first stage of round-robin cells is an input to a next stage of round-robin cells. The round-robin arbiter may transform an arbitration state at each stage of the arbitration and propagate the arbitration state into the next stage for arbitration. The arbitration state from the final stage round-robin cell is fed back to the first stage of the round-robin cells and used in a subsequent arbitration round.
    Type: Application
    Filed: May 17, 2021
    Publication date: November 17, 2022
    Inventors: Shu-Yi YU, Nicolas MELLIS