Patents by Inventor Yi Yu

Yi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220130765
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.
    Type: Application
    Filed: January 5, 2022
    Publication date: April 28, 2022
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Kuei-Ming Chen
  • Publication number: 20220123031
    Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 21, 2022
    Inventors: Min-Ying Tsai, Cheng-Te Lee, Rei-Lin Chu, Ching I Li, Chung-Yi Yu
  • Publication number: 20220115587
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
    Type: Application
    Filed: November 5, 2020
    Publication date: April 14, 2022
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
  • Publication number: 20220115584
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
    Type: Application
    Filed: November 3, 2020
    Publication date: April 14, 2022
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Publication number: 20220115358
    Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
  • Publication number: 20220109104
    Abstract: A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Hai Tao Liu, Li Li Ding, Yao-Hung Liu, Guoan Du, Qi Lu Li, Chunlei Wan, Yi Yu Lin, Yuchao Chen, Huakai Li, Hung-Yueh Chen
  • Publication number: 20220100922
    Abstract: For predicting industrial automation network performance, a method generates algorithm parameters in a first standard format for a network calculus model from design data for a network implementation. The method generates the network calculus model from the algorithm parameters. The network calculus model models worst-case performance for the network implementation. The method generates model parameters in a second standard format for a network simulation model from the design data. The method generates the network simulation model from the model parameters. The network simulation model models probabilistic performance for the network implementation. The method executes the network calculus model to determine network calculus results. The method executes the network simulation model to determine network simulation results. The method determines a system policy difference between the network calculus results, the network simulation results, and the system policy.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Inventors: Yi Yu, Dayin Xu, Mark R. Hantel, Steven A. Zuponcic
  • Publication number: 20220098593
    Abstract: The invention features compositions and methods for treating, reducing, or ameliorating the debilitating effects of Amyotrophic Lateral Sclerosis (ALS) and spinal and bulbar muscular atrophy (SBMA). Provided herein are compositions and methods of using improved new base editors (e.g., adenosine base editors) comprising a polynucleotide programmable nucleotide binding domain and a nucleobase editing domain in conjunction with a guide polynucleotide to disrupt normal transcription of a gene associated with a genetic disease or condition, e.g. ALS, or SBMA by modifying a target gene associated with the genetic disorder or condition with a base editor system provided herein.
    Type: Application
    Filed: February 13, 2020
    Publication date: March 31, 2022
    Applicant: BEAM THERAPEUTICS INC.
    Inventors: Nicole GAUDELLI, Michael PACKER, Ian SLAYMAKER, Yi YU, Bernd ZETSCHE, Jason Michael GEHRKE, Angelica MESSANA, David A. BORN, Seung-Joo LEE
  • Publication number: 20220102621
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Application
    Filed: November 1, 2020
    Publication date: March 31, 2022
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Publication number: 20220098572
    Abstract: The invention features base editors having reduced non-target deamination, methods of using the base editors, and assays for characterizing base editors as having decreased non-target deamination, e.g. compared to programmed, on-target deamination.
    Type: Application
    Filed: January 31, 2020
    Publication date: March 31, 2022
    Applicant: BEAM THERAPEUTICS INC.
    Inventors: Ian SLAYMAKER, Jason Michael GEHRKE, Nicole GAUDELLI, Yi YU
  • Patent number: 11279615
    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hua Lin, Chang-Ming Wu, Chung-Yi Yu, Ping-Yin Liu, Jung-Huei Peng
  • Patent number: 11280015
    Abstract: A fabricating method of a non-enzyme sensor element includes a printing step, a coating step and an electroplating step. In the printing step, a conductive material is printed on a surface of a substrate to form a working electrode, a reference electrode and an auxiliary electrode, and a porous carbon material is printed on the working electrode to form a porous carbon layer. In the coating step, a graphene film material is coated on the porous carbon layer of the working electrode to form a graphene layer. In the electroplating step, a metal is electroplated on the graphene layer by a pulse constant current to form a catalyst layer including a metal oxide.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: March 22, 2022
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Hsiang-Yu Wang, Yi-Yu Chen, Shih-Hao Lin, Yu-Sheng Lin
  • Patent number: 11283330
    Abstract: An integrated apparatus of water-cooled motor and driver includes a motor housing and a driver housing. The motor housing includes a motor-housing inner wall, a motor-housing outer wall, an inlet, a heat-dissipation flow channel and an outlet. The motor-housing inner wall surrounds and receives a motor assembly. The motor-housing outer wall surrounds the motor-housing inner wall, and the exterior thereof has a first connecting surface. The inlet is disposed on the motor-housing outer wall. One end of the heat-dissipation flow channel is connected to the inlet, the end contacts and is received between the motor-housing inner wall and the motor-housing outer wall. The outlet is connected to the other end of the heat-dissipation flow channel and is disposed on the motor-housing outer wall. The driver housing receives a driver assembly, and the exterior thereof has a second connecting surface connected with and bonded to the first connecting surface.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: March 22, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wu-Chen Lin, Chi-Hsiang Kuo, Chien-Chung Shih, Chia-Hsiang Yang, Yi-Yu Lee
  • Publication number: 20220084935
    Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.
    Type: Application
    Filed: September 16, 2020
    Publication date: March 17, 2022
    Inventors: Hsing-Lien Lin, Cheng-Te Lee, Rei-Lin Chu, Chii-Ming Wu, Yeur-Luen Tu, Chung-Yi Yu
  • Publication number: 20220071934
    Abstract: Provided is a pharmaceutical composition for use in treating postsurgical pain. The pharmaceutical composition comprises a lipid-based complex. The lipid-based complex comprises an amide-type anesthetic and at least one lipid, wherein a molar ratio of the amide-type anesthetic to the at least one lipid of the lipid-based complex is at least 0.5:1. The total amount of the amide-type anesthetic is at least 1.5 to 5 times of a standard therapeutic dose for treating postsurgical pain with the amide-type anesthetic to achieve an improved pain control with desired prolonged analgesic effect.
    Type: Application
    Filed: February 26, 2020
    Publication date: March 10, 2022
    Inventors: TIEN-TZU TAI, YUN-LONG TSENG, SHEUE-FANG SHIH, MIN-WEN KUO, CARL OSCAR BROWN, HUI-TING WANG, WEENEE YEUN NG JAO, PEI-HSIEN HU, WAN-NI YU, KEELUNG HONG, HAO-WEN KAO, YI-YU LIN
  • Publication number: 20220069068
    Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 3, 2022
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Chia-Shiung Tsai, Chung-Yi Yu, Rei-Lin Chu
  • Publication number: 20220067391
    Abstract: A method for detecting people entering and leaving a field is provided in an embodiment of the disclosure. The method includes the following. An event detection area corresponding to an entrance is set, and the event detection area includes an upper boundary, a lower boundary, and an internal area, and the lower boundary includes a left boundary, a right boundary, and a bottom boundary; a person image corresponding to a person in an image stream is detected and tracked; and whether the person passes through or does not pass through the entrance is determined according to a first detection result and a second detection result.
    Type: Application
    Filed: December 29, 2020
    Publication date: March 3, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Shu-Hsin Chang, Yao-Chin Yang, Yi-Yu Su, Kun-Hsien Lu
  • Patent number: 11263306
    Abstract: An apparatus, a method, and a system are presented in which the apparatus includes an interface control circuit that may be configured to receive a message including a cryptographic keyword and a policy value. The policy value may include one or more data bits indicative of one or more policies that define allowable usage of the cryptographic keyword. The apparatus also includes a security circuit that may be configured to extract the cryptographic keyword and the policy value from the message, and to apply at least one policy of the one or more policies to usage of the cryptographic keyword in response to a determination that an authentication of the message succeeded.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 1, 2022
    Assignee: Apple Inc.
    Inventors: Timothy R. Paaske, Weihua Mao, Shu-Yi Yu
  • Publication number: 20220061028
    Abstract: A system and method are disclosed that allows for uplink resource reuse. A user device is provided an uplink resource for a first data type. If the user device does not have enough data of the first data type to fill the granted uplink resource, the user device fills the granted uplink resource with a second data type.
    Type: Application
    Filed: September 2, 2021
    Publication date: February 24, 2022
    Inventors: Zhijun Cai, Sean Bartholomew Simmons, James Earl Womack, Takashi Suzuki, Yi Yu
  • Publication number: 20220054455
    Abstract: The present invention relates to a pharmaceutical composition comprising at least one liposome, a trapping agent and a sedative drug with a high drug to lipid ratio and a high encapsulation efficiency. Also provided are the methods to sedate or treat pain in a subject in need thereof by administering the pharmaceutical composition disclosed herein.
    Type: Application
    Filed: September 12, 2019
    Publication date: February 24, 2022
    Inventors: Keelung HONG, Walter GWATHNEY, Hao-wen KAO, Yi-yu LIN