Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: The disclosure provides a method for verifying training data, a training system, and a computer program produce. The method includes: receiving a labelled result with a plurality of bounding regions, wherein the labelled result corresponds to an image, the bounding regions are labelled by a plurality of annotators, the annotators comprises a first annotator and a second annotator, and the bounding region comprises a first bounding region labelled by the first annotator and a second bounding region labelled by the second annotator; and determining the first bounding region and the second bounding region respectively corresponds to different two target objects or corresponds to one target object according to a similarity between the first bounding region and the second bounding region.

Abstract: The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer into a chamber. The method also includes creating an exhaust flow from the chamber. The method further includes depositing a film on the semiconductor wafer by supplying a processing gas into the chamber. In addition, the method includes detecting, with a use of a gas sensor, a concentration of the processing gas in the exhaust flow and generating a detection signal according to a result of the detection. The method further includes supplying a cleaning gas into the processing chamber for a time period after the film is formed on the semiconductor wafer. The time period is determined based on the detection signal.

Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

Abstract: A method, a processing device and a display system for information display are provided. The system includes a display being light transmissive, at least one first information extraction device, at least one second information extraction device, and a processing device. The processing device is connected to the display, the first information extraction device and the second information extraction device. The first information extraction device is configured to extract a user's position information and posture information. The second information extraction device is configured to extract a target object's position information and posture information.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: Method for accessing a wireless network, and terminal device are provided. The method includes the following. When a wireless fidelity (Wi-Fi) module is detected to be disconnected from a wireless network currently accessed, a reason for disconnection between the Wi-Fi module and the wireless network currently accessed is determined. Description information indicating the reason for disconnection between the Wi-Fi module and the wireless network currently accessed is generated and sent to the Wi-Fi module. The description information is received via the Wi-Fi module, and at least one beacon frame is received and recorded within a first preset time period when the description information is determined to be matched with preset description information via the Wi-Fi module. A disconnected wireless network is accessed according to a target beacon frame of the disconnected wireless network when the at least one beacon frame is detected to include the target beacon frame.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Abstract: The present invention relates to a pharmaceutical composition comprising at least one liposome and a therapeutic agent for treating an auto-immune disease with a high therapeutic agent to lipid ratio and a high encapsulation efficiency. The pharmaceutical composition improves the pharmacokinetic profile and sustains the release of the therapeutic agent. Also provided is the method for treating an auto-immune disease using the pharmaceutical composition disclosed herein.

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: Embodiments of this application provide an input apparatus and an electronic device including the input apparatus. The input apparatus includes a top cover, where at least one trench is disposed in a first area of the top cover; a base, where at least one slot group is disposed in a second area of the base, and projections of the second area and the first area in a pressing or tapping direction overlap; a tactile switch, including a force-bearing surface and disposed on the top cover or the base; and at least one connecting rod, disposed between the top cover and the base, where the connecting rod includes a main rod and a side rod group, the main rod is rotatably nested in a corresponding trench, and each side rod in the side rod group is slidably nested in a corresponding slot in the slot group.

Abstract: The present invention relates to pharmaceutical compositions comprising at least one liposome and a therapeutic agent for treating dementia with a high drug to lipid ratio and a high encapsulation efficiency. The pharmaceutical composition improves the pharmacokinetic profile and sustains the release of the therapeutic agent. Also provided is the method for treating dementia using the pharmaceutical composition disclosed herein.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

Abstract: A drying oven for 3D printing materials includes a base, an upper cover, a rotating shaft assembly and a drying assembly. The drying assembly includes a heating plate and a fan. An air outlet end of the fan faces upward, and the heating plate is arranged above the air outlet end of the fan. An accommodating cavity is provided at a middle of the base, and an air inlet communicating with outside is provided at a bottom of the accommodating cavity. The fan and the heating plate are arranged in the accommodating cavity. The rotating shaft assembly is arranged on a top surface of the base. An air outlet is arranged at an upper end of the upper cover, and the upper cover is configured to cover the base.

Abstract: A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of doped polycrystalline silicon layers stacked over one another, and an oxide layer between each adjacent pair of doped polycrystalline silicon layers. A number of the doped polycrystalline silicon layer is ranging from 2 to 6.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

Abstract: The disclosure provides compositions comprising novel adenosine base editors (e.g., ABE8) that have increased efficiency and methods of using these adenosine deaminase variants for editing a target sequence.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.