Abstract: Methods, computer systems, and computer-storage media for transferring ranking signals from equivalent pages to master pages are provided. In embodiments, ranking signals are received. Documents are determined to be equivalent pages. Master pages for the equivalent pages are identified. The ranking signals are transferred to the master pages.

Abstract: The present invention relates to a transparent copolyester, wherein the transparent copolyester comprises an aliphatic-aromatic copolyester segment A, a segment B having repeating units —O—CH(CH3)—C(O)—, and structural units C derived from polyisocyanate(s), wherein the weight ratio for the segment A, segment B and structural unit C is 100:(100-2000):(0.1-10) and wherein the weight-average molecular weight Mw of the transparent copolyester is from 50,000 to 1,000,000. The present invention further relates to a preparation method for a transparent copolyester, including polymerizing lactide, a hydroxyl-terminated aliphatic-aromatic copolyester and a polyisocyanate in the presence of a catalyst; wherein the weight ratio for the aliphatic-aromatic copolyester, lactide and polyisocyanate is 100:(100-2000):(0.1-10). The present invention further relates to a transparent copolyester prepared by said method and an article made from the transparent copolyester according to present invention.

Abstract: The present invention relates to a biodegradable composite and its preparation process, which composite is prepared by mixing feed stocks comprising a polylactic acid, an aliphatic-aromatic copolyester A, an aliphatic-aromatic copolyester B and an organic peroxide at a temperature between about 100 and about 200° C. The present invention also relates to a disposable article, which is prepared from said biodegradable composite.

Abstract: An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate.

Abstract: The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

Abstract: An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate.

Abstract: A device housing is provided. The device housing includes a base device housing, a decorative pattern area, and a plurality of metallic balls. The base device housing defines a plurality of receiving holes. The decorative pattern area is formed in the exterior surface of the base device housing. The metallic balls are positioned in the receiving holes and located inside or outside the decorative pattern area. A method of manufacturing the device housing is also provided.

Abstract: The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

Abstract: An improved network of sensor nodes can self-organize so as to reduce energy consumption and/or improve coverage of a surveillance field. Nodes within the network may be dynamically activated or deactivated so as to lengthen network lifetime and/or enhance sensor coverage of the surveillance field.