Patents by Inventor Yi Zou

Yi Zou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210216697
    Abstract: A method for calibrating a process model and training an inverse process model of a patterning process. The training method includes obtaining a first patterning device pattern from simulation of an inverse lithographic process that predicts a patterning device pattern based on a wafer target layout, receiving wafer data corresponding to a wafer exposed using the first patterning device pattern, and training an inverse process model configured to predict a second patterning device pattern using the wafer data related to the exposed wafer and the first patterning device pattern.
    Type: Application
    Filed: May 23, 2019
    Publication date: July 15, 2021
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Marinus Aart VAN DEN BRINK, Yu CAO, Yi ZOU
  • Patent number: 11003477
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for an apparatus configured to provide I/O classification information in a distributed cloud storage system, in accordance with some embodiments. In one embodiment, the apparatus may include a partition scanner, to scan an image of a virtual disk associated with the storage system, to determine one or more partitions associated with the virtual disk; a file system scanner coupled with the partition scanner, to identify file systems associated with the determined partitions, to access files stored in the identified file systems; and I/O classifier coupled with the file system scanner, to generate I/O classification information associated with the accessed files. The I/O classification information provides characteristics of input-output operations performed on the virtual disk. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Andrew Anderson, Yi Zou
  • Patent number: 10989868
    Abstract: An item such as a fabric-based item may have a layer of fabric such as a layer of woven fabric. The fabric layer may include warp and weft strands. The fabric may cover keys in a keyboard or may be used in forming other structures in the fabric-based item. Each key may have an illuminated key label. Portions of the fabric may be processed by pressing heated protrusions on a textured mold into polymer optical fibers in the fabric. The protrusions form corresponding light-scattering recesses in cladding portions of the optical fibers. Light-emitting diodes or other light sources may be coupled to respective end surfaces of the optical fibers. The light-emitting diodes emit light that is emitted from the thermally imprinted light-emitting regions formed by pressing the heated protrusions into the optical fibers.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 27, 2021
    Assignee: Apple Inc.
    Inventors: Yi Zou, Hua Song, Liming Wang, Daniel A. Podhajny
  • Publication number: 20210103403
    Abstract: Methods and apparatus for end-to-end data plane offloading for distributed storage using protocol hardware and Protocol Independent Switch Architecture (PISA) devices. Hardware-based data plane forwarding is implemented in compute and storage switches that comprise smart server switches running software executing in a kernel and user space. The compute switch is coupled to one or more compute servers/nodes and the storage server is coupled to one or more storage servers or storage arrays. The hardware-based data plane forwarding facilitates an end-to-end data plane between the computer server(s) and storage server(s)/array(s) that is offloaded to hardware. In one example the software comprises Ceph components used to implement control plane operations in connection with hardware offloaded data plane operations, and storage traffic employs the NVMe-oF protocol and the kernels include NVMe-oF modules. In one aspect the hardware-based data plane forwarding is implemented using programmable P4switch chips.
    Type: Application
    Filed: November 9, 2020
    Publication date: April 8, 2021
    Inventors: Shaopeng He, Yadong Li, Ziye Yang, Changpeng Liu, Haitao Kang, Cunming Liang, Gang Cao, Scott Peterson, Sujoy Sen, Yi Zou, Arun Raghunath
  • Patent number: 10972768
    Abstract: In one embodiment, an edge compute node comprises processing circuitry to: receive an incoming video stream captured by a camera, wherein the incoming video stream comprises a plurality of video segments; store the plurality of video segments in a receive buffer in a memory; perform a visual computing task on a first video segment in the receive buffer; detect a resource overload on the edge compute node; receive load information corresponding to a plurality of peer compute nodes; select a peer compute node to perform the visual computing task on a second video segment in the receive buffer; replicate the second video segment from the edge compute node to the peer compute node; and receive a compute result from the peer compute node, wherein the compute result is based on the peer compute node performing the visual computing task on the second video segment.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Yi Zou, Mohammad Ataur Rahman Chowdhury
  • Publication number: 20210048753
    Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.
    Type: Application
    Filed: February 28, 2019
    Publication date: February 18, 2021
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Quan ZHANG, Been-Der CHENG, Rafael C. HOWELL, Jing SU, Yi ZOU, Yen-Wen LU
  • Publication number: 20210004266
    Abstract: A technique is described herein for allocating tasks within a distributed system. The distributed system includes plural computing devices. Each computing device, in turn, provides a bucket manager and at least one application instance. The bucket managers allocate work to the computing devices in units of buckets, in a manner governed by a set of application-specific initialization parameters. The bucket managers also perform their assignment function in cooperation with a separate storage and notification (S&N) system. The S&N system stores data nodes in a hierarchical data structure that reflect the assignment-related state of the distributed system. The S&N system also notifies the bucket managers upon changes in the data nodes. According to one provision, the bucket managers include logic that reduces expensive context changes when computing devices join and leave the distributed system.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 7, 2021
    Inventors: Jia ZHU, Simon Julian POWERS, Paolo CODATO, Yi ZOU, Junaid AHMED
  • Publication number: 20200380362
    Abstract: Methods of training machine learning models related to a patterning process, including a method for training a machine learning model configured to predict a mask pattern. The method including obtaining (i) a process model of a patterning process configured to predict a pattern on a substrate, wherein the process model comprises one or more trained machine learning models, and (ii) a target pattern, and training the machine learning model configured to predict a mask pattern based on the process model and a cost function that determines a difference between the predicted pattern and the target pattern.
    Type: Application
    Filed: February 20, 2019
    Publication date: December 3, 2020
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Yu CAO, Ya LUO, Yen-Wen LU, Been-Der CHEN, Rafael C. HOWELL, Yi ZOU, Jing SU, Dezheng SUN
  • Patent number: 10855766
    Abstract: A method performed by a networking switch in an object storage system. The method includes receiving a first packet from a network comprising an object ID and a data object. The method includes generating a replica for the data object. The method includes generating an object ID for the replica of the data object. The method includes determining a destination storage node for the replica of the data object. The method includes sending a second packet from the networking switch to the destination storage node. The second packet includes the object ID for the replica of the data object and the replica of the data object.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Yi Zou, Arun Raghunath, Anjaneya Reddy Chagam Reddy
  • Publication number: 20200319915
    Abstract: A method is described. The method includes performing the following with a storage end transaction agent within a storage sled of a rack mounted computing system: receiving a request to perform storage operations with one or more storage devices of the storage sled, the request specifying an all-or-nothing semantic for the storage operations; recognizing that all of the storage operations have successfully completed; after all of the storage operations have successfully completed, reporting to a CPU side transaction agent that sent the request that all of the storage operations have successfully completed.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Arun RAGHUNATH, Yi ZOU, Tushar Sudhakar GOHAD, Anjaneya R. CHAGAM REDDY, Sujoy SEN
  • Patent number: 10764389
    Abstract: Technologies for managing replica caching in a distributed storage system include a storage manager device. The storage manager device is configured to receive a data write request to store replicas of data. Additionally, the storage manager device is configured to designate one of the replicas as a primary replica, select a first storage node to store the primary replica of the data in a cache storage and at least a second storage node to store a non-primary replica of the data in a non-cache storage. The storage manager device is further configured to include a hint in a first replication request to the first storage node that the data is to be stored in the cache storage of the first storage node as the primary replica. Further, the storage manager device is configured to transmit replication requests to the respective storage nodes. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Arun Raghunath, Michael Mesnier, Yi Zou
  • Patent number: 10670973
    Abstract: A method includes obtaining a sub-layout having an area that is a performance limiting spot, adjusting colors of patterns in the area, and determining whether the area is still a performance limiting spot. Another method includes decomposing patterns in a design layout into multiple sub-layouts; determining for at least one area in one of the sub-layouts, the likelihood of that a figure of merit is beyond its allowed range; and if the likelihood is above a threshold, that one sub-layout has a performance limiting spot. Another method includes: obtaining a design layout having a first group of patterns and a second group of patterns, wherein colors of the first group of patterns are not allowed to change and colors of the second group of patterns are allowed to change; and co-optimizing at least the first group of patterns, the second group of patterns and an illumination of a lithographic apparatus.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: June 2, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Yi Zou, Jing Su, Robert John Socha, Christopher Alan Spence, Duan-Fu Stephen Hsu
  • Patent number: 10629932
    Abstract: An apparatus monitors the state of charge (SOC) of a flow battery system. The monitoring method include determining SOCs of at least two pairs of different monitoring positions. A pair of monitoring position may be located inside of an anode electrolyte storage tank (2) and inside of a cathode electrolyte storage tank (3), or inside of an anode electrolyte outlet pipeline (6) of a stack and inside of a cathode electrolyte outlet pipeline (7) of the stack, or inside of an anode electrolyte inlet pipeline (8) of the stack and inside of a cathode electrolyte inlet pipeline (9) of the stack. The SOCsum of the flow battery system is acquired according to the SOCs corresponding to different pair of monitoring positions, respectively. The method ensures acquiring an SOC monitoring result timely and accurately.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: April 21, 2020
    Assignee: DALIAN RONGKEPOWER CO., LTD
    Inventors: Yu Zhang, Yi Zou, Huamin Zhang, Ying Li, Xiaoli Wang, Xi Han, Lecong Han, Tao Zhang, Xiangkun Ma, Honggui Zhao
  • Publication number: 20200050099
    Abstract: A method including: obtaining a portion of a design layout; determining characteristics of assist features based on the portion or characteristics of the portion; and training a machine learning model using training data including a sample whose feature vector includes the characteristics of the portion and whose label includes the characteristics of the assist features. The machine learning model may be used to determine characteristics of assist features of any portion of a design layout, even if that portion is not part of the training data.
    Type: Application
    Filed: May 4, 2018
    Publication date: February 13, 2020
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jing SU, Yi ZOU, Chenxi LIN, Yu CAO, Yen-Wen LU, Been-Der CHEN, Quan ZHANG, Stanislas Hugo Louis BARON, Ya LUO
  • Publication number: 20200026655
    Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Zhe WANG, Alaa R. Alameldeen, Yi Zou, Gordon King
  • Publication number: 20200029086
    Abstract: In one embodiment, an apparatus comprises processing circuitry to: receive, via a communication interface, a frame of a video stream; determine a number of subframes to be encoded in parallel for the frame; partition the frame into a plurality of subframes based on the number of subframes to be encoded in parallel; and send, via the communication interface, the plurality of subframes to a cluster of encoding servers, wherein the cluster of encoding servers is to encode the plurality of subframes in parallel, and wherein each subframe of the plurality of subframes is to be encoded by a particular encoding server of the cluster of encoding servers.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Yi Zou, Gang Shen, Jun Tian
  • Patent number: 10503654
    Abstract: Methods and apparatus related to framework and/or methodology for selective caching of Erasure Coded fragments in a distributed storage system are described. In one embodiment, a plurality of fragments of a data object are generated. Each of the plurality of fragments is Erasure Coded (EC) prior to storage at a storage node of a plurality of storage nodes. Each of the plurality of fragments is transmitted with a caching hint to indicate whether that fragment is to be cached at the storage node. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Arun Raghunath, Michael P. Mesnier, Yi Zou
  • Publication number: 20190348331
    Abstract: A method where deviations of a characteristic of an image simulated by two different process models or deviations of the characteristic simulated by a process model and measured by a metrology tool, are used for various purposes such as to reduce the calibration time, improve the accuracy of the model, and improve the overall manufacturing process.
    Type: Application
    Filed: December 13, 2017
    Publication date: November 14, 2019
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Yu CAO, Yi ZOU, Chenxi LIN
  • Publication number: 20190327506
    Abstract: In one embodiment, an edge compute node comprises processing circuitry to: receive an incoming video stream captured by a camera, wherein the incoming video stream comprises a plurality of video segments; store the plurality of video segments in a receive buffer in a memory; perform a visual computing task on a first video segment in the receive buffer; detect a resource overload on the edge compute node; receive load information corresponding to a plurality of peer compute nodes; select a peer compute node to perform the visual computing task on a second video segment in the receive buffer; replicate the second video segment from the edge compute node to the peer compute node; and receive a compute result from the peer compute node, wherein the compute result is based on the peer compute node performing the visual computing task on the second video segment.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Yi Zou, Mohammad Ataur Rahman Chowdhury
  • Publication number: 20190325227
    Abstract: In one embodiment, an apparatus comprises processing circuitry to: receive, via a network interface, a video stream comprising a plurality of video frames; identify a plurality of dependencies among the plurality of video frames; identify, based on the plurality of dependencies, a first subset of video frames to be transmitted using a first transmission method and a second subset of video frames to be transmitted using a second transmission method, wherein the first subset of video frames and the second subset of video frames are identified from the plurality of video frames, and wherein the first transmission method provides a higher quality of service than the second transmission method; transmit, via the network interface, the first subset of video frames to a corresponding destination using the first transmission method; and transmit, via the network interface, the second subset of video frames to the corresponding destination using the second transmission method.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventors: Ned M. Smith, Yi Zou, Shao-Wen Yang, Gang Shen