Patents by Inventor Yi Zou

Yi Zou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10095424
    Abstract: Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the non-volatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: October 9, 2018
    Assignee: INTEL CORPORATION
    Inventors: Wei Wu, Yi Zou, Jawad B. Khan, Xin Guo
  • Patent number: 10083742
    Abstract: Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller organizes the storage cells into storage cell groups, each storing m bits of information programmed with the threshold voltage levels. A determination is made of one threshold voltage level to use for each of the storage cells in the storage cell group to program a selected k bits in the storage cell group with threshold voltage levels defining one of a plurality of valid states. The threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 25, 2018
    Assignee: INTEL CORPORATION
    Inventors: Wei Wu, Jawad B. Khan, Sanjeev N. Trika, Yi Zou
  • Publication number: 20180259857
    Abstract: A method includes obtaining a sub-layout having an area that is a performance limiting spot, adjusting colors of patterns in the area, and determining whether the area is still a performance limiting spot. Another method includes decomposing patterns in a design layout into multiple sub-layouts; determining for at least one area in one of the sub-layouts, the likelihood of that a figure of merit is beyond its allowed range; and if the likelihood is above a threshold, that one sub-layout has a performance limiting spot. Another method includes: obtaining a design layout having a first group of patterns and a second group of patterns, wherein colors of the first group of patterns are not allowed to change and colors of the second group of patterns are allowed to change; and co-optimizing at least the first group of patterns, the second group of patterns and an illumination of a lithographic apparatus.
    Type: Application
    Filed: April 29, 2016
    Publication date: September 13, 2018
    Inventor: Yi ZOU
  • Patent number: 10063555
    Abstract: Methods, apparatus, and systems for achieving privilege separation are provided herein. In an exemplary method, an operation-applying instruction sent by a first-type client can be received. According to the operation-applying instruction, it can be determined whether an operation corresponding to the operation-applying instruction is able to be executed. When the operation corresponding to the operation-applying instruction is able to be executed, an operation-executing instruction can be sent to a second-type client, such that the second-type client can obtain a privilege for executing the operation, according to the operation-executing instruction. A notifying instruction can be sent to a third-type client, such that the third-type client can obtain a notification that the second-type client has obtained the privilege for executing the operation.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: August 28, 2018
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yi Zou, Lei Gao
  • Patent number: 10043573
    Abstract: Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: August 7, 2018
    Assignee: INTEL CORPORATION
    Inventors: Wei Wu, Yi Zou, Jawad B. Khan, Xin Guo
  • Publication number: 20180090201
    Abstract: Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller organizes the storage cells into storage cell groups, each storing m bits of information programmed with the threshold voltage levels. A determination is made of one threshold voltage level to use for each of the storage cells in the storage cell group to program a selected k bits in the storage cell group with threshold voltage levels defining one of a plurality of valid states. The threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels.
    Type: Application
    Filed: September 26, 2016
    Publication date: March 29, 2018
    Inventors: Wei WU, Jawad B. KHAN, Sanjeev N. TRIKA, Yi ZOU
  • Publication number: 20180060242
    Abstract: Methods and apparatus related to framework and/or methodology for selective caching of Erasure Coded fragments in a distributed storage system are described. In one embodiment, a plurality of fragments of a data object are generated. Each of the plurality of fragments is Erasure Coded (EC) prior to storage at a storage node of a plurality of storage nodes. Each of the plurality of fragments is transmitted with a caching hint to indicate whether that fragment is to be cached at the storage node. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 1, 2016
    Publication date: March 1, 2018
    Applicant: Intel Corporation
    Inventors: Arun Raghunath, Michael P. Mesnier, Yi Zou
  • Publication number: 20180039429
    Abstract: Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the non-volatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 8, 2018
    Inventors: Wei WU, Yi ZOU, Jawad B. KHAN, Xin GUO
  • Publication number: 20180040367
    Abstract: Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 8, 2018
    Inventors: Wei WU, Yi ZOU, Jawad B. KHAN, Xin GUO
  • Publication number: 20170251073
    Abstract: Technologies for managing replica caching in a distributed storage system include a storage manager device. The storage manager device is configured to receive a data write request to store replicas of data. Additionally, the storage manager device is configured to designate one of the replicas as a primary replica, select a first storage node to store the primary replica of the data in a cache storage and at least a second storage node to store a non-primary replica of the data in a non-cache storage. The storage manager device is further configured to include a hint in a first replication request to the first storage node that the data is to be stored in the cache storage of the first storage node as the primary replica. Further, the storage manager device is configured to transmit replication requests to the respective storage nodes. Other embodiments are described and claimed.
    Type: Application
    Filed: February 29, 2016
    Publication date: August 31, 2017
    Inventors: Arun Raghunath, Michael Mesnier, Yi Zou
  • Publication number: 20170237091
    Abstract: An apparatus monitors the state of charge (SOC) of a flow battery system. The monitoring method include determining SOCs of at least two pairs of different monitoring positions. A pair of monitoring position may be located inside of an anode electrolyte storage tank (2) and inside of a cathode electrolyte storage tank (3), or inside of an anode electrolyte outlet pipeline (6) of a stack and inside of a cathode electrolyte outlet pipeline (7) of the stack, or inside of an anode electrolyte inlet pipeline (8) of the stack and inside of a cathode electrolyte inlet pipeline (9) of the stack. The SOCsum of the flow battery system is acquired according to the SOCs corresponding to different pair of monitoring positions, respectively. The method ensures acquiring an SOC monitoring result timely and accurately.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventors: Yu ZHANG, Yi ZOU, Huamin ZHANG, Ying LI, Xiaoli WANG, Xi HAN, Lecong HAN, Tao ZHANG, Xiangkun MA, Honggui ZHAO
  • Patent number: 9531653
    Abstract: Systems and methods are provided for user group management. For example, a contracting invitation for joining a user group and a first identifier of a first user from a first terminal associated with an administrator of the user group are received; a contracting-invitation page including a first indication message to request the first user to join the user group and a first interface element for inputting a contracting acceptance is generated; the contracting-invitation page is displayed on a second terminal associated with the first user to allow the first user to input the contracting acceptance via the interface element; the contracting acceptance is received from the second terminal; and the first identifier of the first user is added to a user list corresponding to the user group.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: December 27, 2016
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventors: Yi Zou, Lei Gao
  • Publication number: 20160180416
    Abstract: Disclosed are a method and apparatus for quitting a user group, which includes: receiving from a first terminal corresponding to a user a user identifier, a contract cancellation command input by the user and a group identifier of a user group to which the user belongs; acquiring a contract time length corresponding to the user identifier, and judging whether the user meets a contract cancellation condition or not according to the contract time length; if the user meets the contract cancellation condition, generating a contract cancellation confirmation page, the contract cancellation confirmation page including an interface interaction element for inputting a contract cancellation confirmation command; displaying the contract cancellation confirmation page on the first terminal; receiving the contract cancellation confirmation command from the first terminal; and deleting the user identifier from a user list of the user group, so that the rate of user loss of a voice communication platform may be lowered, an
    Type: Application
    Filed: February 26, 2016
    Publication date: June 23, 2016
    Inventor: Yi Zou
  • Publication number: 20160142414
    Abstract: Methods, apparatus, and systems for achieving privilege separation are provided herein. In an exemplary method, an operation-applying instruction sent by a first-type client can be received. According to the operation-applying instruction, it can be determined whether an operation corresponding to the operation-applying instruction is able to be executed. When the operation corresponding to the operation-applying instruction is able to be executed, an operation-executing instruction can be sent to a second-type client, such that the second-type client can obtain a privilege for executing the operation, according to the operation-executing instruction. A notifying instruction can be sent to a third-type client, such that the third-type client can obtain a notification that the second-type client has obtained the privilege for executing the operation.
    Type: Application
    Filed: January 22, 2016
    Publication date: May 19, 2016
    Inventors: Yi Zou, Lei Gao
  • Publication number: 20160142883
    Abstract: Methods and program products of mobile device location estimation using categorized local location data from various sources. For example, a method includes: detecting one or more wireless access gateways on a mobile device; for at least one detected wireless access gateway, determining whether or not location data of the gateway exists among part or all of a predetermined collection of data on the mobile device, the location data including a location estimate of the gateway, and none or at least one of: an uncertainty value associated with the location estimate; or a confidence value related to the likelihood that the gateway is stationary; determining whether or not a condition related to location estimation of the device is true; determining a location estimate of the device using the existing location data of the detected gateways on the device or other location estimation methods, based on the determination of the condition.
    Type: Application
    Filed: November 15, 2014
    Publication date: May 19, 2016
    Inventors: Jian Zou, Yi Zou
  • Patent number: 9305800
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask. The photomask defines an assisting lithographically-printable mask feature. A block copolymer is deposited into the assisting etch resistant fill confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The assisting etch resistant fill topographical features direct the etch resistant phase to form an etch resistant plug in the assisting etch resistant fill confinement well.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Tamer Coskun, Wei-Long Wang, Azat Latypov, Yi Zou
  • Patent number: 9286434
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Yi Zou, Wei-Long Wang, Azat Latypov, Tamer Coskun
  • Patent number: 9208275
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes inputting DSA target patterns. The DSA target patterns are grouped into groups including a first group and a group boundary is defined around the first group as an initial OPC mask pattern. A circle target is generated around each of the DSA target patterns in the first group to define a merged circle target boundary. The initial OPC mask pattern is adjusted and/or iteratively updated using the merged circle target boundary to generate an output final OPC mask pattern.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Wei-Long Wang, Azat Latypov, Yi Zou, Tamer Coskun
  • Publication number: 20150339429
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Yi Zou, Wei-Long Wang, Azat Latypov, Tamer Coskun
  • Patent number: 9170501
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes using a computing system, inputting a DSA target pattern and an initial pattern. An output mask writer pattern is produced from the initial pattern using the computing system, the DSA target pattern, a DSA model, an OPC model, and a MPC model. The output mask writer pattern is for a mask writer to write on the photomask.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Azat Latypov, Yi Zou, Vito Dai