Patents by Inventor Yibin Ye

Yibin Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9669672
    Abstract: A trailer coupler may be provided with an opening and socket for a hitch ball, and a clamping bar in an internal channel for locking the coupler and hitch together. The internal channel may extend horizontally and be positioned above the opening and below the socket. The channel may include a laterally-facing aperture adjacent the second end, out of which one end of the clamping bar may extend. That end of the clamping bar may include a bracket with an open channel to fit over a flange on the coupler body. The coupler may be assembled by inserting a first end of the clamping bar through the laterally-facing aperture, and moving the first end of the clamping bar into the coupler body channel while fitting the bracket over the flange at the open channel of the clamping bar.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: June 6, 2017
    Assignee: Pacific Rim International, LLC
    Inventor: Yibin Ye
  • Publication number: 20160152103
    Abstract: A trailer coupler may be provided with an opening and socket for a hitch ball, and a clamping bar in an internal channel for locking the coupler and hitch together. The internal channel may extend horizontally and be positioned above the opening and below the socket. The channel may include a laterally-facing aperture adjacent the second end, out of which one end of the clamping bar may extend. That end of the clamping bar may include a bracket with an open channel to fit over a flange on the coupler body. The coupler may be assembled by inserting a first end of the clamping bar through the laterally-facing aperture, and moving the first end of the clamping bar into the coupler body channel while fitting the bracket over the flange at the open channel of the clamping bar.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Applicant: Pacific Rim International, LLC
    Inventor: Yibin YE
  • Patent number: 9254723
    Abstract: A trailer coupler may be provided with an opening and socket for a hitch ball, and a clamping bar in an internal channel for locking the coupler and hitch together. The internal channel may extend horizontally and be positioned above the opening and below the socket. The channel may include a laterally-facing aperture adjacent the second end, out of which one end of the clamping bar may extend. That end of the clamping bar may include a bracket with an open channel to fit over a flange on the coupler body. The coupler may be assembled by inserting a first end of the clamping bar through the laterally-facing aperture, and moving the first end of the clamping bar into the coupler body channel while fitting the bracket over the flange at the open channel of the clamping bar.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: February 9, 2016
    Assignee: Pacific Rim International, LLC
    Inventor: Yibin Ye
  • Publication number: 20140300084
    Abstract: A trailer coupler may be provided with an opening and socket for a hitch ball, and a clamping bar in an internal channel for locking the coupler and hitch together. The internal channel may extend horizontally and be positioned above the opening and below the socket. The channel may include a laterally-facing aperture adjacent the second end, out of which one end of the clamping bar may extend. That end of the clamping bar may include a bracket with an open channel to fit over a flange on the coupler body. The coupler may be assembled by inserting a first end of the clamping bar through the laterally-facing aperture, and moving the first end of the clamping bar into the coupler body channel while fitting the bracket over the flange at the open channel of the clamping bar.
    Type: Application
    Filed: June 9, 2014
    Publication date: October 9, 2014
    Applicant: PACIFIC RIM INTERNATIONAL, LLC
    Inventor: Yibin YE
  • Patent number: 8769376
    Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Patent number: 8746726
    Abstract: A trailer coupler may be provided with an opening and socket for a hitch ball, and a clamping bar in an internal channel for locking the coupler and hitch together. The internal channel may extend horizontally and be positioned above the opening and below the socket. The channel may include a laterally-facing aperture adjacent the second end, out of which one end of the clamping bar may extend. That end of the clamping bar may include a bracket with an open channel to fit over a flange on the coupler body. The coupler may be assembled by inserting a first end of the clamping bar through the laterally-facing aperture, and moving the first end of the clamping bar into the coupler body channel while fitting the bracket over the flange at the open channel of the clamping bar.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: June 10, 2014
    Assignee: Pacific Rim International, LLC
    Inventor: Yibin Ye
  • Patent number: 8667367
    Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: March 4, 2014
    Assignee: Intel Corporation
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Publication number: 20130024752
    Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.
    Type: Application
    Filed: September 25, 2012
    Publication date: January 24, 2013
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Publication number: 20120306180
    Abstract: A trailer coupler may be provided with an opening and socket for a hitch ball, and a clamping bar in an internal channel for locking the coupler and hitch together. The internal channel may extend horizontally and be positioned above the opening and below the socket. The channel may include a laterally-facing aperture adjacent the second end, out of which one end of the clamping bar may extend. That end of the clamping bar may include a bracket with an open channel to fit over a flange on the coupler body. The coupler may be assembled by inserting a first end of the clamping bar through the laterally-facing aperture, and moving the first end of the clamping bar into the coupler body channel while fitting the bracket over the flange at the open channel of the clamping bar.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicant: PACIFIC RIM INTERNATIONAL, LLC
    Inventor: Yibin YE
  • Patent number: 8283771
    Abstract: In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 9, 2012
    Assignee: Intel Corporation
    Inventors: Dinesh Somasekhar, Tanay Karnik, Jianping Xu, Yibin Ye
  • Publication number: 20110307761
    Abstract: For one disclosed embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments are also disclosed.
    Type: Application
    Filed: August 23, 2011
    Publication date: December 15, 2011
    Inventors: Khellah Muhammad, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Patent number: 8006164
    Abstract: For one embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments have one or more other features.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: August 23, 2011
    Assignee: Intel Corporation
    Inventors: Khellah Muhammad, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Patent number: 7684520
    Abstract: A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 23, 2010
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Muhammad M. Khellah, Yibin Ye, Vivek K. De
  • Patent number: 7653846
    Abstract: For one embodiment, an apparatus may include a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also include first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments include other apparatuses, methods, and systems.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: January 26, 2010
    Assignee: Intel Corporation
    Inventors: Nam Sung Kim, Muhammad Kheliah, Yibin Ye, Dinesh Somasekhar, Vivek De
  • Publication number: 20090321893
    Abstract: In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Dinesh Somasekhar, Tanay Karnik, Jianping Xu, Yibin Ye
  • Patent number: 7558097
    Abstract: For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: July 7, 2009
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Patent number: 7532528
    Abstract: A memory system having a selectable configuration for sense amplifiers is included. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Dinesh Somasekhar, Muhammad M Khellah, Yibin Ye, Nam Sung Kim, Vivek K De
  • Patent number: 7514746
    Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Brian Doyle, Suman Datta, Vivek K. De
  • Patent number: 7501316
    Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Stephen H. Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • Publication number: 20090003108
    Abstract: In one embodiment, a memory system having a selectable configuration for sense amplifiers is disclosed. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.
    Type: Application
    Filed: June 30, 2007
    Publication date: January 1, 2009
    Inventors: Dinesh Somasekhar, Muhammad M. Khellah, Yibin Ye, Nam Sung Kim, Vivek K. De