Patents by Inventor Yibin Ye

Yibin Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7230842
    Abstract: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Nam Sung Kim, Yibin Ye, Vivek K. De, Kevin Zhang, Bo Zheng
  • Patent number: 7206249
    Abstract: A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 17, 2007
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, James Tschanz, Stephen H. Tang, Vivek K. De
  • Publication number: 20070076463
    Abstract: According to embodiments of the present invention, a one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. In on embodiment, access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
  • Patent number: 7200068
    Abstract: A multi-ported register comprises a Global Bit Line (GBL) to couple a gate to a data output line via an output transistor. A Local bit Line (LBL) couples the gate to a first register file cell and a second register file cell, said second register file cell disposed closer to the data output line than the first register file cell. At least one transistor in the first register file cell having a stronger drive current than the at least one transistor in the second register file cell. At least one of, the output transistor, the gate, and the first register file cell of a first bank have a stronger drive current than the corresponding output transistor, the gate and the first register file cell of a second bank said second bank being closer to the data output line.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: April 3, 2007
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Yibin Ye, Stephen H. Tang, Vivek De
  • Publication number: 20070058419
    Abstract: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 15, 2007
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Nam Kim, Yibin Ye, Vivek De, Kevin Zhang, Bo Zheng
  • Patent number: 7183795
    Abstract: Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Yibin Ye, James W. Tschanz, Muhammad M. Khellah, Vivek K. De
  • Publication number: 20070024322
    Abstract: A method and system for leakage current reduction in domino circuits is described. The system includes a domino circuit with a dynamic gate, a static gate, and a standby signal to set the domino circuit to an evaluate phase during an inactive mode. The inputs to the static gate are set to low and the inputs to the dynamic gate are set to high during the inactive mode. The standby signal may be an input to a device in the dynamic gate or an input to a latch coupled to the dynamic gate.
    Type: Application
    Filed: August 1, 2005
    Publication date: February 1, 2007
    Inventors: Yibin Ye, Siva Narendra, Vivek De
  • Patent number: 7167397
    Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: January 23, 2007
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De, Tanay Karnik
  • Publication number: 20070002611
    Abstract: A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is read by asserting a signal on a word line that is coupled to the cell and to another group of cells in the array, in a direction of, but without reaching, the first voltage. Other embodiments are also described and claimed.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Yibin Ye, Muhammad Khellah, Dinesh Somasekhar, Ali Keshavarzi, Fabrice Paillet, Vivek De
  • Publication number: 20070002607
    Abstract: In some embodiments, a memory array is provided comprising columns of SRAM bit cells, the columns each comprising a bit line and a sense amplifier coupled to the bit line, the sense amplifier to maintain a state in a selected cell of its bit line during a read operation. Other embodiments are disclosed herein.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De
  • Publication number: 20070004162
    Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20060291265
    Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Dinesh Somasekhar, Yibin Ye, Ali Keshavarzi, Muhammad Khellah, Vivek De
  • Publication number: 20060285393
    Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De, Tanay Karnik
  • Publication number: 20060279985
    Abstract: In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.
    Type: Application
    Filed: June 14, 2005
    Publication date: December 14, 2006
    Inventors: Ali Keshavarzi, Stephen Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Vivek De, Gerhard Schrom
  • Publication number: 20060268626
    Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: May 25, 2005
    Publication date: November 30, 2006
    Inventors: Fatih Hamzaoglu, Kevin Zhang, Nam Kim, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De, Bo Zheng
  • Publication number: 20060267093
    Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
    Type: Application
    Filed: May 4, 2006
    Publication date: November 30, 2006
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Brian Doyle, Suman Datta, Vivek De
  • Publication number: 20060262610
    Abstract: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
    Type: Application
    Filed: May 23, 2005
    Publication date: November 23, 2006
    Applicant: Intel Corporation
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De, James Tschanz, Stephen Tang
  • Patent number: 7123500
    Abstract: A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: Yibin Ye, Dinesh Somasekhar, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi, Shih-Lien L. Lu, Vivek K. De
  • Patent number: 7120072
    Abstract: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: Yibin Ye, Dinesh Somasekhar, Muhammad M Khellah, Fabrice Paillet, Stephen H Tang, Ali Keshavarzi, Shih-Lien L Lu, Vivek K De
  • Patent number: 7120804
    Abstract: An approach for power reduction of an integrated circuit device. In response to detecting a change in an activity factor associated with an integrated circuit device from a first activity factor to a second activity factor, a supply voltage and a body bias associated with the integrated circuit device are adjusted based on the second activity factor to reduce power consumption. For one aspect, the supply voltage and body bias are adjusted to maintain a substantially constant operating frequency for the integrated circuit device.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Yibin Ye, Liqiong Wei, Vivek K. De