Abstract: A flip-flop circuit comprising a first stage having a transmission gate to receive a data signal from an input node, and a second stage connected to the first stage, the second stage having another transmission gate to transfer the data signal to a memory unit, wherein the memory unit provides complementary output signals.

Abstract: A stack device is provided to obtain a stack effect. The stack device includes at least first and second active components. The first and second active components have first and second device widths, respectively. The first and second device widths are then selected to provide a desired leakage current and gate delay time for the stack device. The selection includes adjusting the first and second device widths while keeping a sum of the device widths constant.

Abstract: A stack device is provided to obtain a stack effect. The stack device includes at least first and second active components. The first and second active components have first and second device widths, respectively. The first and second device widths are then selected to provide a desired leakage current and gate delay time for the stack device. The selection includes adjusting the first and second device widths while keeping a sum of the device widths constant.

Abstract: A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage which serves as an output receiver circuit, the output of which is the output of the domino logic circuit. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.

Abstract: A domino logic circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage, the output of which is the output of the domino logic circuit. A p-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. A pull-up circuit is connected between the static CMOS circuit output and the high voltage connection.

Abstract: A method and apparatus for transmitting data through a CMOS bus line includes a pulse generator to generate a pulse representing a data signal, and a decoder for receiving the pulse and an output port for delivering the detected signal to a receiving device.

Abstract: A method and apparatus for reducing leakage current in an integrated circuit includes a supply voltage line, a virtual supply voltage line, a ground voltage line, a virtual ground voltage line, a first logic circuit coupled to the ground voltage line and selectively coupled to the virtual supply voltage line, a second logic circuit coupled to the supply voltage line and selectively coupled to the virtual ground voltage line, and a switch circuit configured to control the selective coupling of the first logic circuit to the virtual supply line voltage and the second logic circuit to the virtual ground voltage line.

Abstract: An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.

Abstract: A domino logic circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage, the output of which is the output of the domino logic circuit. A p-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. A pull-up circuit is connected between the static CMOS circuit output and the high voltage connection.

Abstract: A dual level voltage shifter includes several series connections of transistors, and cross coupled pairs of transistors, to provide dual-level voltage shifting with low power consumption and low static current. In another embodiment, a dual level voltage shifter includes an inverter with current limiting diodes, and cross coupled inverters with a pass gate in their feedback loop, also providing low power consumption and low static current.

Abstract: A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, with the gate of the clock transistor coupled to receive an inverse clock signal. A first inverter and a second inverter are connected in series such that the input of the first inverter is connected to the output of the second inverter. The input of the second inverter is connected to the dynamic output node. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection.

Abstract: In some embodiments, the invention includes a domino gate including a domino stage node and an evaluate network. The evaluate network includes a first group of transistors coupled between the domino stage node and a voltage reference node. The gate also includes a second group of transistors coupled between respective ones of inputs of the first group of transistors and the voltage reference node. The gate may be a precharge domino gate or a predischarge domino gate. The gate may comprise a pull-up transistor coupled to the domino stage node, the pull-up transistor including an input to receive a clock signal (Clk) and wherein the second group of transistors have inputs to receive a clock signal (Clk*), which is an inverse of Clk. Clk may lead or trial Clk*.

Abstract: A circuit and method for reducing noise in a memory circuit is disclosed. In one embodiment, the circuit includes an amplifier, a first transistor and a second transistor. The first transistor is capable of pulling up a first input port of the amplifier in response to a complement of the second memory signal. The second transistor is capable of pulling of a second input port of the amplifier in response to a complement of the first memory signal. In one embodiment, the method includes receiving a first memory signal at a first input port of an amplifier, receiving a second memory signal at a second input port of the amplifier, and pulling up the second input port in response to a complement of the first memory signal.

Abstract: Standby leakage reduction circuitry that uses boosted gate drive of a leakage control transistor during an active mode. A circuit block includes a first leakage control transistor coupled to receive a first supply voltage and coupled in series with an internal circuit block that performs a particular function. A gate drive circuit is included to apply a first boosted gate drive voltage to a gate of the first leakage control transistor during an active mode of the internal circuit block. The gate drive circuit furthers applies a standby gate voltage to the gate during a standby mode of the internal circuit block, the standby gate voltage to cause a gate to source voltage of the leakage control transistor to be reverse-biased.

Abstract: Standby leakage reduction circuitry that uses boosted gate drive of a leakage control transistor during an active mode. A circuit block includes a first leakage control transistor coupled to receive a first supply voltage and coupled in series with an internal circuit block that performs a particular function. A gate drive circuit is included to apply a first boosted gate drive voltage to a gate of the first leakage control transistor during an active mode of the internal circuit block. The gate drive circuit furthers applies a standby gate voltage to the gate during a standby mode of the internal circuit block, the standby gate voltage to cause a gate to source voltage of the leakage control transistor to be reverse-biased.

Abstract: A domino logic circuit includes input connections to receive a clock signal and an input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising at least one n-channel pull-up transistor having a gate coupled to receive the input data signal. The n-channel pull-up transistor has a low threshold voltage. The dynamic stage can include an n-channel pull-down transistor which has a gate connection coupled to receive the clock signal. First and second inverter circuits can also be provided to latch a voltage on a drain of the pull-down transistor. Static logic circuits coupled to the dynamic stage have skewed rise and fall times to increase the propagation time of the domino circuit.

Abstract: A domino logic circuit includes input connections to receive a clock signal and an input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising at least one n-channel pull-up transistor having a gate coupled to receive the input data signal. The n-channel pull-up transistor has a low threshold voltage. The dynamic stage can include an n-channel pull-down transistor which has a gate connection coupled to receive the clock signal. First and second inverter circuits can also be provided to latch a voltage on a drain of the pull-down transistor. Static logic circuits coupled to the dynamic stage have skewed rise and fall times to increase the propagation time of the domino circuit.

Abstract: A domino logic circuit includes input connections to receive a clock signal and at least one input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising precharge circuitry, and a static stage that comprises discharge circuitry. In another embodiment, the domino logic circuit includes a dynamic stage comprising discharge circuitry, and a static stage that comprises precharge circuitry. Different configurations and transistor types have also been described. The circuitry can provide improved speed performance, or increase noise immunity.

Abstract: A dual level voltage shifter includes several series connections of transistors, and cross coupled pairs of transistors, to provide dual-level voltage shifting with low power consumption and low static current. In another embodiment, a dual level voltage shifter includes an inverter with current limiting diodes, and cross coupled inverters with a pass gate in their feedback loop, also providing low power consumption and low static current.

Abstract: A technique for reducing standby leakage current in a circuit block using input vector activation. A complex circuit includes a plurality of inputs and one or more transistor stacks. At least some of the transistor stacks are coupled to at least one of the inputs. The circuit also includes logic to apply a selected input vector to the plurality of inputs during a standby mode. The input vector is selected based on a configuration of the one or more transistor stacks in the circuit block to turn off a first number of transistors in the transistor stacks. The first number is within a selected percent of a maximum number of transistors in the transistor stacks that can be turned off by any vector applied at the plurality of inputs.