Abstract: A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.

Abstract: A photoresist stripping apparatus and a corresponding method for removing photoresist layers after a patterned polyimide layer is developed. The photoresist-stripping apparatus includes a transporting unit, a stripping unit, a washing unit, a drying unit and a control unit. The transporting unit connects the stripping unit, the washing unit and the drying unit. The control unit is responsible for controlling the transport sequence and timing of the transporting unit. The method of stripping the photoresist layer off the OLED panel includes providing a stripping solution to the stripping unit to remove photoresist layers. The OLED panel is jet-cleaned with a washing solution in the washing unit so that any residual stripping agent is removed. Finally, the surface of the OLED panel is blown dry.

Abstract: A charged-device model (CDM) electrostatic discharge (ESD) protection for complementary metal oxide semiconductor (CMOS) integrated circuits such as input/output (I/O) circuits. A CDM ESD clamp device is disposed on an output buffer or an input stage of the CMOS circuit in order to clamp the CDM ESD overstress voltage across the gate oxide during a CDM ESD event. When applied to I/O circuits, a bi-directional diode string with multiple diodes is used in conjunction with the CDM ESD clamp device. During the CDM ESD event, CDM charges (CDM Q) originally stored in the common substrate are discharged through the desired CDM ESD clamp device so as to protect all functional devices in the input, output or I/O circuits, and effectively improve the CDM ESD level in integrated circuit (IC) products.

Abstract: A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and instead of a dummy gate. Thereby, the SCR device has a narrower anode-to-cathode spacing, and then the lateral SCR device can be turned on more quickly to protect the CMOS IC's in ESD events. Additionally, the silicon area of the substrate occupied by the lateral SCR device is also saved. This method for forming a lateral SCR device without shallow-trench-isolation regions in its current path can be fully process-compatible to general CMOS technologies by only changing layout patterns in the mask layers.

Abstract: A method and an apparatus for transporting substrates in all organic light emitting diode (OLED) process is disclosed, which has a transferring chamber provided for transporting substrates between processing modules and the atmosphere condition therein is able to be adjusted to be the same as the processing module by an atmosphere conditioner unit. According to the present invention, the substrates are not contaminated by moisture and the process operation and the factory layout are more flexible. Moreover, the OLED yield is improved.

Abstract: An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions.

Abstract: An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions.

Abstract: A bonding pad structure to avoid probing damage applied to IC or PCB products comprises a first pad and at least one second pad. The first pad is coupled with the second pad. The first pad is used for wire bonding & packaging while the second pad is used for probing in IC function testing. Therefore, it avoids the probing damage of the first pad after the IC function testing and further increases the IC reliability while wire bonding & packaging.

Abstract: An integrated circuit device that includes a plurality of electrostatic discharge clamp circuits, variously coupled to VDD, VSS and transistor, having at least one bi-directional silicon diode that includes a first silicon diode and a second silicon diode, wherein an n-type portion of the first silicon diode is coupled to a p-type portion of the second silicon diode and a p-type portion of the first silicon diode is coupled to an n-type portion of the second silicon diode, responsive to either a positive electrostatic discharge or a negative electrostatic discharge to provide electrostatic discharge protection.

Abstract: A method and an apparatus for transporting substrates in an organic light emitting diode (OLED) process is disclosed, which has a transferring chamber provided for transporting substrates between processing modules and the atmosphere condition therein is able to be adjusted to be the same as the processing module by an atmosphere conditioner unit. According to the present invention, the substrates are not contaminated by moisture and the process operation and the factory layout are more flexible. Moreover, the OLED yield is improved.

Abstract: A mass-production packaging means suitable for mass-production packaging of an organic luminescent display. An organic electroluminescent display panel on which an organic luminescent device has been formed is first provided. Then, an UV laser is used to clean the surface of the organic electroluminescent display panel. A molding compound is applied on the organic electroluminescent display panel by a sizing system. Subsequently, a lid is aligned with the organic electroluminescent display panel and lamination is performed. Finally, the molding compound is irradiated with UV light to be cured. The package is thus completed.

Abstract: An apparatus for developing a pixel-defining layer of an organic light emitting diode (OLED) display panel. The apparatus has a developing unit, a cleaning unit, a drying unit, a conveying unit and a control unit. The conveying unit transports the display panel to each of the connected units. The control unit determines a conveying order and a conveying time of the conveying unit so as to precisely control a processing time of the display panel in each of the units connected with the conveying unit. The conveying unit continuously transports the display panel to the developing unit, the cleaning unit and the drying unit in sequence to complete the developing process. Thereby, the apparatus can precisely control the predetermined developing time, the quality of pixel-defining layers and effectively reduce the period of the developing process and the labor cost.

Abstract: A method of the invention for forming a pixel-defining layer on an OLED panel is disclosed.

Abstract: A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing.

Abstract: An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one destination processor associated therewith for servicing the interrupt request. An interrupt controller in accordance with the present invention applies latched interrupt requests to a priority compare tree which serves to prioritize received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. Similar determinations are made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt.

Abstract: A check is made to determine if a copy of a cache line is currently resident in the level-one data cache of a microprocessor system. If, in response to the check, it is determined that a copy of such cache line in fact is not currently resident, the cache line is created as the least-recently used cache line. Then, for set-associative data caches, the next used of the associative set will replace the most recently zeroed line. In this way, zeroing operations can replace only one .div. (number of associative sets) of the data cache for zeroing operations, thereby leaving the most frequently used data intact. By doing so, the data-cache is not wasted on zeroed cache lines which may be infrequently reused from the data cache, thereby significantly improving system performance. In other words the net effect is to reduce probability of data cache misses on subsequent instructions because more of the cache is thereby made available for more frequently reused data.

Abstract: A method and apparatus are provided for generating a ratioed clock signal. A first clock signal having a first frequency is output. At least one gating signal indicating ratio is output. In response to the first clock signal and the gating signal, a second clock signal is output. The second clock signal has a frequency that is substantially related to the first frequency by the ratio.

Abstract: An electrical shock apparatus includes a power source, a high voltage generation device for generating a very high voltage to shock a robber in response to a connection to the power source, an alarm device for generating an alarming sound to shock a robber in response to a connection to the power source, a function selection switch switchably connecting the power source to either the high voltage generation device, the alarm device, or an empty connection. A pin-socket switch is connected between the power source, the function selection switch, and the alarm device. The pin-socket switch includes a socket and a pin removably received in the socket. Normally, the pin of the pin-socket switch is retained in the socket and electrically connects the function selection switch to the power source yet separates the alarm device from the power source. The function selection switch electrically connects the power source to the empty connection via the pin-socket switch in normal condition.

Abstract: An automatic size-grading and shrimp peeling machine for shrimps; the automatic grading machine includes a plate-partition conveyer mounted to a slanting platform; the slanting platform is mounted with at least three conveying screw shafts coupled with the plate-partition conveyer and a plurality of feeding pipes of peeling machine. The automatic grading machine is mounted on a machine supporting frame so as to have all feeding ports mounted over the peeling machine, which includes at least three peeling units; each unit includes a large swing peeling roller and two small revolving peeling rollers; a pressing roller and at least one squeezing wheel are mounted between two small revolving peeling rollers. The squeezing wheel and the pressing roller are mounted in parallel each other, but perpendicular to the small revolving peeling rollers.