Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.

Abstract: A method for manufacturing a semiconductor device includes forming a source/drain region on a semiconductor fin. The source/drain region is adjacent to a dummy gate. The method further includes forming a first dielectric layer over the source/drain region and the dummy gate. The first dielectric layer has a dielectric constant of 3.5 or less. The first dielectric layer may include boron nitride or silicon dioxide with Si—CH3 bonds.

Abstract: Disclosed are methods of manufacturing semiconductor devices that include the operations of forming an isolation structure in a semiconductor substrate, forming an active region adjacent the isolation structure, forming at least two primary polysilicon structures over the active region, the primary polysilicon structures defining a contacted polysilicon pitch (CPP), and forming a secondary polysilicon structure over the isolation structure. In some methods, the secondary polysilicon structure is further modified and/or replaced in order to provide additional functional elements on the semiconductor devices.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: Some implementations described herein provide techniques and apparatuses for determining a performance of a dry-clean operation within a deposition tool. A cleaning-control subsystem of the deposition tool may include a gas concentration sensor and a temperature sensor mounted in an exhaust system of the deposition tool to monitor the dry-clean operation. The gas concentration sensor may provide data related to a concentration of a chemical compound in a cleaning gas, where the chemical compound is a bi-product of the dry-clean operation. The temperature sensor may provide temperature data related to an exothermic reaction of the dry-clean operation. Such data may be used to determine an efficiency and/or an effectiveness of the dry-clean operation within the deposition tool.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: An electronic device includes a memory usage identification circuit and a system-level cache (SLC). The memory usage identification circuit obtains a memory usage indicator that depends on memory usage of a storage space allocated in a system memory at which memory access is requested by a physical address. The SLC includes a cache memory and a cache controller. The cache controller performs cache management upon the cache memory according to the physical address and the memory usage indicator.

Abstract: A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.

Abstract: A method for making a semiconductor device includes: forming a first gate stack over a first fin; forming a first gate spacer extending along a side of the first gate stack; forming a second gate spacer over the first gate spacer; forming a third gate spacer over the second gate spacer, the third gate spacer; forming a source/drain region adjacent the third gate spacer; depositing an interlayer dielectric (ILD) over the source/drain region, the ILD including a third dielectric material; and removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD. The void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD. The void includes a horizontal portion extending beneath the source/drain region.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: A semiconductor device is provided, which includes a semiconductor stack and a first contact structure. The semiconductor stack includes an active layer and has a first surface and a second surface. The first contact structure is located on the first surface and includes a first semiconductor layer, a first metal element-containing structure and a first p-type or n-type layer. The first metal element-containing structure includes a first metal element. The first p-type or n-type layer physically contacts the first semiconductor layer and the first metal element-containing structure. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm, and the first semiconductor layer includes a phosphide compound or an arsenide compound.

Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a first chip, a second chip and a conductive structure. The first chip has an active side and an opposite side disposed opposite to each other. The second chip includes a chip bonding portion and an outer pad, and the outer pad is located outside the chip bonding portion. The first chip is disposed on the chip bonding portion of the second chip with the active side. The conductive structure is disposed on the outer pad, and the conductive structure includes a stack of a plurality of metal balls. The stack extends from the outer pad beyond the opposite side of the first chip.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A display apparatus and an image processing method thereof are provided. The display apparatus includes a display panel and an image processing device. The image processing device receives a low-resolution image from a host. The image processing device tracks a user's gaze to define a region of interest (ROI). The image processing device performs a video super-resolution (VSR) reconstruction on an original ROI image corresponding to the ROI in the low-resolution image to generate a high-definition ROI image. The image processing device pastes the high-definition ROI image back to the ROI in the low-resolution image to generate a processed image. The image processing device controls the display panel to display the processed image.

Abstract: The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.

Abstract: The present invention relates to an electronic device pick-and-place system and an electronic device testing apparatus having the same, comprising a plurality of pick-and-place heads, a plurality of negative pressure generators and an air pressure regulating valve. Each pick-and-place head has a pick-and-place port; the plurality of negative pressure generators are communicated with the plurality of pick-and-place ports of the plurality of pick-and-place heads respectively; an inlet end of the air pressure regulating valve is communicated with an air pressure source, and an outlet end of the air pressure regulating valve is communicated with the plurality of negative pressure generators; the air pressure regulating valve can be used to adjust the suction forces of the pick-and-place ports of the pick-and-place heads in a batch. Accordingly, the suction forces and blowing forces of the pick-and-place ports of the pick-and-place heads can be adjusted in a batch.

Abstract: The treatment system provides a feature that may reduce cost of the electrochemical plating process by reusing the virgin makeup solution in the spent electrochemical plating bath. The treatment system provides a rotating filter shaft which receives the spent electrochemical plating bath and captures the additives and by-products created by the additives during the electrochemical plating process. To capture the additives and the by-products, the rotating filter shaft includes one or more types of membranes. Materials such as semi-permeable membrane are used to capture the used additives and by-products in the spent electrochemical plating bath. The treatment system may be equipped with an electrochemical sensor to monitor a level of additives in the filtered electrochemical plating bath.