Patents by Inventor Yin Lin

Yin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255062
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: November 14, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 12256519
    Abstract: An immersion cooling system includes a cooling tank, a housing and a valve. The coolant tank is configured to accommodate a liquid coolant and an electronic device immersed in the liquid coolant. The housing covers a side of the cooling tank and thereby forms an enclosure. The valve has two ports, one of which communicates with the enclosure and the other communicates with a part of the cooling tank above the liquid coolant. The valve is configured to open in response to a gas pressure inside the cooling tank exceeding an upper limit.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: March 18, 2025
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Chih Lin, Ren-Chun Chang, Yan-Hui Jian, Chia-Hsing Chen, Li-Hsiu Chen, Wen-Yin Tsai
  • Patent number: 12248164
    Abstract: A backlight module includes a light guide plate, a light source, and an optical film. The light guide plate has a light incident surface and a light exiting surface opposite to the light incident surface, in which the light exiting surface has a normal line. The light source is adjacent to the light incident surface. The optical film is disposed to the light exiting surface and includes plural parallel prisms and plural microstructures. An extending direction of each of the prisms is perpendicular to the normal line, and each of the prisms faces the light exiting surface of the light guide plate. Each of the microstructures is located on a surface of the optical film which faces away from the light guide plate. Each of the microstructures has a pyramid structure with plural facets. The prisms are located between the microstructures and the light exiting surface.
    Type: Grant
    Filed: January 26, 2024
    Date of Patent: March 11, 2025
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: Chia-Yin Chang, Po-Chang Huang, Kun-Cheng Lin
  • Publication number: 20250081572
    Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a first semiconductor material disposed over a substrate and a dielectric layer disposed on the first semiconductor material. The dielectric layer includes a dopant. The structure further includes a second semiconductor material disposed on the dielectric layer, a first semiconductor layer in contact with the second semiconductor material, and a first dielectric spacer in contact with the first semiconductor layer, wherein the first dielectric spacer includes the dopant.
    Type: Application
    Filed: January 3, 2024
    Publication date: March 6, 2025
    Inventors: Yu-Chang LIN, Po-Kang HO, Liang-Yin CHEN, Tsai-Yu HUANG, Chi On CHUI
  • Publication number: 20250079853
    Abstract: A power generating device and a power supplying method thereof are provided. The power generating device includes a battery set, a charge storage device, a charger and a voltage converter. The battery set has microbial fuel cell and/or solar battery, and is configured to generate a supply voltage. The charger generates a charging voltage according to the supply voltage, and provides the charging voltage through a first resistor to charge the charge storage device. The voltage converter converts a storage voltage provided by the charge storage device to generate a driving voltage, and provides the driving voltage to drive a load.
    Type: Application
    Filed: October 20, 2023
    Publication date: March 6, 2025
    Applicant: National Tsing Hua University
    Inventors: Chao-I Liu, Heng-An Su, I-Chu Lin, Yao-Yu Lin, Chia-Chieh Hsu, Hsin-Tien Li, Tzu-Yin Liu, Han-Yi Chen
  • Publication number: 20250079227
    Abstract: A wafer retaining device is provided. The wafer retaining device includes a platen configured to support a semiconductor wafer, and a retainer assembly. The retainer assembly includes a mounting member coupled to the platen, a lever, and a biasing member including a first end coupled to the lever and a second end coupled to the mounting member. The biasing member is configured to bias the lever to a closed position relative to the platen. The lever inhibits movement of the semiconductor wafer when the lever is in the closed position.
    Type: Application
    Filed: January 18, 2024
    Publication date: March 6, 2025
    Inventors: Lu-Hsun LIN, Tsung-Min LIN, Chin Tsung LIN, Hsiao-Yin HSIEH, Po-Tang TSENG
  • Publication number: 20250079492
    Abstract: A plant microbial fuel cell includes a planting container, a plant, a cathode and an anode. The planting container has a culture medium therein, and a microbial population is in the culture medium. The plant is grown in the culture medium in the planting container. The cathode is disposed on a surface of the culture medium, and the anode is arranged in the culture medium close to roots of the plant. The anode includes a porous carbon material prepared from coffee grounds, and thus the overall cost of the plant microbial fuel cell may be greatly reduced, and the porous carbon material is easy to process and has high biocompatibility.
    Type: Application
    Filed: October 19, 2023
    Publication date: March 6, 2025
    Applicant: National Tsing Hua University
    Inventors: Yao-Yu Lin, Hsin-Tien Li, Heng-An Su, Tzu-Yin Liu, Han-Yi Chen
  • Publication number: 20250079237
    Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 12237417
    Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Publication number: 20250058324
    Abstract: An automated molecular operating system includes at least one centrifuge tube carrying module, a transport module, a plurality of temperature control modules, a capping module, a magnetic field module and an automated processing module. The automated processing module is electrically connected to the transport module, the temperature control modules, the capping module and the magnetic field module, and controls the transport module to move the centrifuge tube carrying module, so that a centrifuge tube contained in the centrifuge tube carrying module makes a reaction in the temperature control modules, and the magnetic field module or the capping module is provided to the centrifuge tube according to requirements, such that a specimen in the centrifuge tube can be automatically subjected to nucleic acid extraction, nucleic acid amplification, primer labeling, reverse transcription or a combination thereof, thereby reducing manual operation errors and increasing the ease of operation.
    Type: Application
    Filed: November 17, 2023
    Publication date: February 20, 2025
    Inventors: Yi-Fang CHEN, Suz-Kai HSIUNG, Chun-Wei HUANG, Yin-Lin LI, Yu-Ying WU
  • Publication number: 20250052511
    Abstract: A vapor chamber heatsink assembly, under vacuum, having a working fluid therein, comprising a plurality of heatsink fins and a vapor chamber is provided. The vapor chamber comprises an upper and lower casing having an upper and lower chamber surface, respectively. The upper and lower chamber surfaces define a plurality of obstructers forming a plurality of braided channels therearound. When heat from a greater temperature heat source and a lower temperature heat source is applied to respective contact surfaces of the lower casing, via the plurality of obstructers and braided channels, respectively, the working fluid and liquid vapor slugs/bubbles travel therethrough, providing an effective phase change mechanism to the greater temperature heat source, while concurrently, hindering agglomeration of working fluid thereto. An effective phase change mechanism is also concurrently provided to the lower temperature heat source due to the non-agglomeration of working fluid to the greater temperature heat source.
    Type: Application
    Filed: October 24, 2024
    Publication date: February 13, 2025
    Inventors: Chia yu Lin, Shan yin Cheng, Chien ting Liu
  • Publication number: 20250056852
    Abstract: A method includes forming first nanostructures over a substrate, then forming second nanostructures over the plurality of first nanostructures. A first source/drain region is epitaxially grown adjacent the first nanostructures, and a second source/drain region is epitaxially grown over the first source/drain region and adjacent the second nanostructures. An implantation process is performed to implant impurities into the second source/drain region, wherein the implantation process forms an amorphous region within the second source/drain region. At least one rapid thermal process is performed on the second source/drain region, wherein performing each rapid thermal process recrystallizes a portion of the amorphous region.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Inventors: Yu-Chang Lin, Liang-Yin Chen, Chi On Chui
  • Publication number: 20250041264
    Abstract: The object of the present disclosure is to provide a method for treating diabetes by using an Antrodia camphorata compound, wherein the Antrodia camphorata compound is shown in the following formula 1: or the pharmacologically acceptable salts of the formula 1.
    Type: Application
    Filed: January 24, 2024
    Publication date: February 6, 2025
    Inventors: Mao-tien Kuo, Yin-yu Kuo, Hui-ling Tseng, Tai-lin Tseng, Wan-ping Tseng, Yi-ling Ye, Li-shian Shi, Ya-hong Lin
  • Publication number: 20250048763
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Publication number: 20250044708
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun LIU, Huicheng CHANG, Chia-Cheng CHEN, Jyu-Horng SHIEH, Liang-Yin CHEN, Shu-Huei SUEN, Wei-Liang LIN, Ya Hui CHANG, Yi-Nien SU, Yung-Sung YEN, Chia-Fong CHANG, Ya-Wen YEH, Yu-Tien SHEN
  • Patent number: 12218216
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Liang Lu, Chang-Yin Chen, Chih-Han Lin, Chia-Yang Liao
  • Patent number: 12218196
    Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chang Lin, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12210023
    Abstract: The present invention discloses an ?-synuclein sensing film, a manufacturing method and a use thereof. The ?-synuclein sensing film comprises a base plate and plural ?-synuclein sensing polymers polymerized on the base plate. Each of the plural ?-synuclein sensing polymers has plural ?-synuclein detection holes on a surface thereof. The plural ?-synuclein sensing polymers are manufactured by electropolymerization, and the plural ?-synuclein detection holes are imprinted by an ?-synuclein peptide. A sample to be tested can be applied to the ?-synuclein sensing film for detecting the ?-synuclein therein.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: January 28, 2025
    Assignee: National University of Kaohsiung
    Inventors: Hung-Yin Lin, Shyh-Chyang Luo, Mei-Hwa Lee, Zi-Lin Su
  • Patent number: 12211750
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang
  • Publication number: 20250030258
    Abstract: An electronic pendant for pet includes a pendant body, a light belt, a battery management module, and a display screen. The pendant body is provided with an accommodated cavity for receiving a battery for supplying power, an outer edge of the pendant body is provided with a transparent structure that can transmit light. The light strip is fixed in the transparent structure and is electrically connected with the battery. The battery management module includes a processor and an electricity meter, in which the electricity meter is electrically connected to the battery to measure the remaining electric quantity of the battery, and the processor is electrically connected to the electricity meter to output a measurement result of the electricity meter. The display screen is arranged on the front surface of the pendant body and is electrically connected to the processor to display the measurement result of the electricity meter.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventor: Yin Lin