Patents by Inventor Yin Lin

Yin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087934
    Abstract: A method for operating a conveying system is provided. An overhead hoist transport (OHT) vehicle is provided, wherein the OHT vehicle includes a gripping member configured to grip and hold a carrier, and a receiver configured to receive a signal. The signal is transmitted to the receiver of the OHT vehicle. The OHT vehicle is moved toward the carrier, and the carrier is gripped by the gripping member of the OHT vehicle. A lifting force is determined based on a weight of a carrier, a number of workpieces in the carrier, or a vertical distance between the OHT vehicle and the carrier, and the lifting force is applied to the carrier.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Inventors: YONG-JYU LIN, FU-HSIEN LI, CHEN-WEI LU, CHI-FENG TUNG, HSIANG YIN SHEN
  • Publication number: 20240087879
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11929419
    Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11922563
    Abstract: A system and method for creating, managing, and displaying 3D digital collectibles comprising a virtual, three dimensional, n-sided structure including a digital media file or set of digital media files representing an event rendered on a representation of at least a first surface thereof, and data relating to the event rendered on at least a second surface thereof and other content on one or more other surfaces, where the digital media file may be video clip of the event that can be played automatically via a media player associated with the display.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: March 5, 2024
    Assignee: Dapper Labs, Inc.
    Inventors: Donald Dundas McEroy Flavelle, Catherine Marzi Tedman, Courtney McNeil, Denise Cascelli Schwenck Bismarque, Christopher Patrick Scott, Alan Carr, Eric Yu-Yin Lin
  • Patent number: 11921314
    Abstract: A backlight module includes a light guide plate, a light source, and an optical film. The light guide plate has a light incident surface and a light exiting surface opposite to the light incident surface, in which the light exiting surface has a normal line. The light source is adjacent to the light incident surface. The optical film is disposed to the light exiting surface and includes plural parallel prisms and plural microstructures. An extending direction of each of the prisms is perpendicular to the normal line, and each of the prisms faces the light exiting surface of the light guide plate. Each of the microstructures is located on a surface of the optical film which faces away from the light guide plate. Each of the microstructures has a pyramid structure with plural facets. The prisms are located between the microstructures and the light exiting surface.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: March 5, 2024
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: Chia-Yin Chang, Po-Chang Huang, Kun-Cheng Lin
  • Publication number: 20240071799
    Abstract: A system for a semiconductor fabrication facility comprises a transporting tool configured to move a carrier, a first manufacturing tool configured to accept the carrier facing in a first direction, a second manufacturing tool configured to accept the carrier facing in the second direction, and an orientation tool. The carrier is moved to the orientation tool by the transporting tool prior to being moved to the first manufacturing tool or the second manufacturing tool by the transporting tool. The orientation tool rotates the carrier so that the carrier is accepted by the first manufacturing tool or the second manufacturing tool. The transporting tool, the first manufacturing tool, the second manufacturing tool and the orientation tool are physically separated from each other.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: CHUAN WEI LIN, FU-HSIEN LI, YONG-JYU LIN, RONG-SHEN CHEN, CHI-FENG TUNG, HSIANG YIN SHEN
  • Publication number: 20240072180
    Abstract: Structures for a varactor diode and methods of forming same. The structure comprises a first semiconductor layer including a section on a substrate, a second semiconductor layer on the section of the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a doped region in the section of the first semiconductor layer. The section of the first semiconductor layer and the doped region have a first conductivity type, and the second semiconductor layer comprises silicon-germanium having a second conductivity type opposite to the first conductivity type, and the third semiconductor layer has the second conductivity type. The doped region contains a higher concentration of a dopant of the first conductivity type than the section of the first semiconductor layer. The second semiconductor layer abuts the first section of the first semiconductor layer along an interface, and the doped region is positioned adjacent to the interface.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Saloni Chaurasia, Jeffrey Johnson, Vibhor Jain, Crystal R. Kenney, Sudesh Saroop, Teng-Yin Lin, John J. Pekarik
  • Publication number: 20240074119
    Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.
    Type: Application
    Filed: May 9, 2023
    Publication date: February 29, 2024
    Inventors: Ren-Chun CHANG, Wei-Chih LIN, Sheng-Chi WU, Wen-Yin TSAI, Li-Hsiu CHEN
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Patent number: 11915818
    Abstract: A system for assessing extubation includes a respiratory assistance device, an artificial intelligence platform, and a hospital information system. The respiratory assistance device is adapted to communicate with a trachea of a patient. The artificial intelligence platform includes a prediction module. A method for assessing extubation includes the following steps. Measured values of respiratory parameters of the patient are recorded by the respiratory assistance device. The recorded times and the measured values of the respiratory parameters corresponding to each of the recording times are transmitted to the artificial intelligence platform. The prediction module analyzes the measured values of respiratory parameters within a predetermined time period according to a prediction model to generate a prediction result. The prediction result is transmitted to the hospital information system and is recorded into a medical record of the patient.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: February 27, 2024
    Assignee: Changhua Christian Medical Foundation Changhua Christian Hospital
    Inventors: Kuo-Yang Huang, Ying-Lin Hsu, Yin-Tzer Shih
  • Publication number: 20240063078
    Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second semiconductor die, a thermal spreader, a molding material, and a second redistribution layer. The first semiconductor die and the second semiconductor die are disposed side-by-side over the first redistribution layer. The thermal spreader vertically overlaps with the first semiconductor die and/or the second semiconductor die. The molding material surrounds the thermal spreader, the first semiconductor die and the second semiconductor die. The second redistribution layer is disposed over the molding material.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: Che-Hung KUO, Chun-Yin LIN
  • Patent number: 11899419
    Abstract: An integrated control management system includes an input output device. The input output device includes a database, a memory module, a first processing module, and a second processing module. The memory module receives and stores a plurality of integrated control commands, and one of the integrated control commands is generated based on a hardware control command for setting a hardware control transmitted by another input and output device. The first processing module reads the integrated control command from the memory module and obtains the hardware control data from the integrated control command. The first processing module updates the hardware control data to the database. The second processing module reads the database and updates the hardware control data stored in the database to another database in another input output device. The second processing module sets the hardware control based on the hardware control data stored in the database.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: February 13, 2024
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventors: Heng-Chia Hsu, Chen-Yin Lin, Yu-Shu Yeh, Chien-Chung Wang, Chin-Hung Tan
  • Patent number: 11883777
    Abstract: Asymmetric hollow fiber membranes, membrane contactors, and related production and use methods. The asymmetric hollow fiber membranes include a porous substrate having a multiplicity of pores, the porous substrate including at least a first semi-crystalline thermoplastic polyolefin copolymer derived by polymerizing at most 3 wt. % of linear or branched alpha olefin monomers with at least 97 wt. % of 4-methyl-1-pentene monomer. The asymmetric hollow fiber membranes also include a skin layer overlaying the porous substrate, the skin layer including a second semi-crystalline thermoplastic polyolefin copolymer derived by polymerizing at least 2 wt. % of linear or branched alpha olefin monomers with at most 98 wt. % of 4-methyl-1-pentene monomer. The skin layer is less porous than the porous substrate and forms an outer surface of the asymmetric hollow fiber membrane, while the porous substrate forms an inner surface of the hollow fiber membrane. The skin layer is preferably nonporous.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: January 30, 2024
    Assignee: 3M Innovative Properties Company
    Inventors: Kuan-Yin Lin, James C. DeLozier, Mark McCormick, Aurore Y. J. Mercelat, Jinsheng Zhou
  • Patent number: 11865666
    Abstract: An apparatus for performing chemical mechanical polish on a wafer includes a polishing head that includes a retaining ring. The polishing head is configured to hold the wafer in the retaining ring. The retaining ring includes a first ring having a first hardness, and a second ring encircled by the first ring, wherein the second ring has a second hardness smaller than the first hardness.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: January 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chien Hou, Ching-Hong Jiang, Kuo-Yin Lin, Ming-Shiuan She, Shen-Nan Lee, Teng-Chun Tsai, Yung-Cheng Lu
  • Publication number: 20230407252
    Abstract: Provided herein are methods, kits and reagents for analyzing the attributes of cell populations, such as donor cells prior to modification to provide engineered cells, e.g., engineered immune cells, such as CAR T cells. For example, provided herein are methods of determining the amount or percentage of biomarkers and/or secretion profiles of donor cell populations, selecting donor cells with certain biomarkers and/or secretion profiles, and engineering the CAR T cells from the selected donor cells.
    Type: Application
    Filed: April 28, 2023
    Publication date: December 21, 2023
    Inventors: Meng-Yin LIN, Hayung YOON, Thomas Charles PERTEL, Barbra Johnson SASU
  • Patent number: 11847467
    Abstract: A boot method for an embedded system is provided. The embedded system includes two mainboards each provided with a baseboard management controller (BMC), a non-volatile memory unit and a network adapter. When the embedded system is turned on, each of the BMCs performs a boot procedure, and then loads an operating system (OS) image file from a corresponding non-volatile memory unit to execute an operating system. When one BMC fails to load the OS image file or to execute the operating system, the BMC causes the corresponding network adapter to communicate with the other network adapter to acquire the OS image file from the non-volatile memory unit on the other mainboard, so as to replace the OS image file in the corresponding non-volatile memory unit, and directly loads the OS image thus acquired to execute the operating system.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: December 19, 2023
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventors: Yu-Shu Yeh, Heng-Chia Hsu, Chen-Yin Lin, Chien-Chung Wang, Chin-Hung Tan
  • Patent number: 11831165
    Abstract: A hierarchical control method for an island power grid energy storage system for increasing new energy generation fluctuation is disclosed. The method includes implementing a rolling dispatch method based on an idea of model predictive control; comprehensively considering a response capability of the energy storage system to grid-wide economic dispatch instructions and life loss of energy storage lithium batteries, and constructing an objective function of an intraday control model of the energy storage system with economic optimization; and constructing, on a basis of satisfying the objective function of the intraday control model, a real-time control model of the energy storage system and solving the model, and determining charge and discharge plans of a lithium battery energy storage system and a supercapacitor energy storage system.
    Type: Grant
    Filed: October 11, 2020
    Date of Patent: November 28, 2023
    Assignee: STATE GRID ZHEJIANG ELECTRIC POWER CO., LTD. TAIZHOU POWER SUPPLY COMPANY
    Inventors: Jian Yang, Jianhua Lv, Guode Ying, Zuofu Jiang, Xin Wang, Haohua Wu, Yongling Li, Jianjun Zhu, Daojian Hong, Haili Liang, Huiqi Chen, Qingxi Cai, Baorong Liu, Yiting Hu, Xingbai Wang, Chuhang Xu, Lijun Zhu, Qiang Gao, Xinghui Jiang, Xiaofei Wang, Yin Lin, Xun Ma
  • Publication number: 20230372400
    Abstract: Disclosed are compositions comprising an isolated chimeric interleukin 6 receptor alpha (IL-6R?) binding protein or cells expressing an isolated chimeric IL-6R? binding protein. The isolated IL-6R? chimeric binding protein and cells expressing the protein may be used in methods of treating cancer and reducing the risk of cytokine release syndrome.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 23, 2023
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Yvonne Yu-Hsuan CHEN, Meng-Yin LIN
  • Publication number: 20230310320
    Abstract: The present disclosure provides a soluble microcarrier, including soluble polymer including a plurality of soluble monomers binding to each other with a reducing crosslinking agent. The soluble microcarrier of present disclosure facilitates the attachment of cells, and reducing agents can facilitate the detachment of cells. When the soluble microcarrier is in contact with a reducing agent, the soluble microcarrier degrades.
    Type: Application
    Filed: May 11, 2022
    Publication date: October 5, 2023
    Inventors: Hsieh-Chih TSAI, Shuian-Yin LIN, Ming-Chien YANG, Chun-Chiang HUANG, Yu-Hsuan LIN
  • Publication number: 20230307316
    Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface. A semiconductor device is mounted on the top surface of the substrate. The semiconductor device has an active front surface directly facing the substrate, and an opposite rear surface. A vapor chamber lid is in thermal contact with the rear surface of the semiconductor device. The vapor chamber lid includes an internal vacuum-sealed cavity that stores a working fluid, and wick structures for recirculating the working fluid within the internal vacuum-sealed cavity.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 28, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chin-Lai Chen, Wei-Che Huang, Wen-Sung Hsu, Chun-Yin Lin, Li-Song Lin, Tai-Yu Chen