Abstract: A battery power measuring system for a Battery-Backed SRAM includes a nonvolatile memory (11), a clock (12), a CPU (10) and a buzzer (13). The nonvolatile memory is for storing a system time, an estimated battery maximal endurance, an estimated battery minimal endurance, and a cumulative on-battery run time. The clock is for indicating the current system time. The CPU is for calculating a new cumulative on-battery run time and a remaining battery endurance. The buzzer is for reminding users to replace a battery when the remaining battery endurance is lower than the estimated battery minimal endurance. The CPU is connected to the nonvolatile memory, the clock, and the buzzer through a plurality of data buses (14). A related battery power measuring method is also provided.

Abstract: A post processing de-blocking filter includes a threshold determination unit for adaptively determining a plurality of threshold values according to at least differences in quantization parameters QPs of a plurality of adjacent blocks in a received video stream and to a user defined offset (UDO) allowing the threshold levels to be adjusted according to the UDO value; an interpolation unit for performing an interpolation operation to estimate pixel values in an interlaced field if the video stream comprises interlaced video; and a de-blocking filtering unit for determining a filtering range specifying a maximum number of pixels to filter around a block boundary between the adjacent blocks, determining a region mode according to local activity around the block boundary, selecting one of a plurality of at least three filters, and filtering a plurality of pixels around the block boundary according to the filtering range, the region mode, and the selected filter.

Abstract: A post processing de-blocking filter includes a threshold determination unit for adaptively determining a plurality of threshold values according to at least differences in quantization parameters QPs of a plurality of adjacent blocks in a received video stream and to a user defined offset (UDO) allowing the threshold levels to be adjusted according to the UDO value; an interpolation unit for performing an interpolation operation to estimate pixel values in an interlaced field if the video stream comprises interlaced video; and a de-blocking filtering unit for determining a filtering range specifying a maximum number of pixels to filter around a block boundary between the adjacent blocks, determining a region mode according to local activity around the block boundary, selecting one of a plurality of at least three filters, and filtering a plurality of pixels around the block boundary according to the filtering range, the region mode, and the selected filter.

Abstract: A post processing de-blocking filter includes a threshold determination unit for adaptively determining a plurality of threshold values according to at least differences in quantization parameters QPs of a plurality of adjacent blocks in a received video stream and to a user defined offset (UDO) allowing the threshold levels to be adjusted according to the UDO value; an interpolation unit for performing an interpolation operation to estimate pixel values in an interlaced field if the video stream comprises interlaced video; and a de-blocking filtering unit for determining a filtering range specifying a maximum number of pixels to filter around a block boundary between the adjacent blocks, determining a region mode according to local activity around the block boundary, selecting one of a plurality of at least three filters, and filtering a plurality of pixels around the block boundary according to the filtering range, the region mode, and the selected filter.

Abstract: A post processing de-blocking filter includes a threshold determination unit for adaptively determining a plurality of threshold values according to at least differences in quantization parameters QPs of a plurality of adjacent blocks in a received video stream and to a user defined offset (UDO) allowing the threshold levels to be adjusted according to the UDO value; an interpolation unit for performing an interpolation operation to estimate pixel values in an interlaced field if the video stream comprises interlaced video; and a de-blocking filtering unit for determining a filtering range specifying a maximum number of pixels to filter around a block boundary between the adjacent blocks, determining a region mode according to local activity around the block boundary, selecting one of a plurality of at least three filters, and filtering a plurality of pixels around the block boundary according to the filtering range, the region mode, and the selected filter.

Abstract: A post processing de-blocking filter includes a threshold determination unit for adaptively determining a plurality of threshold values according to at least differences in quantization parameters QPs of a plurality of adjacent blocks in a received video stream and to a user defined offset (UDO) allowing the threshold levels to be adjusted according to the UDO value; an interpolation unit for performing an interpolation operation to estimate pixel values in an interlaced field if the video stream comprises interlaced video; and a de-blocking filtering unit for determining a filtering range specifying a maximum number of pixels to filter around a block boundary between the adjacent blocks, determining a region mode according to local activity around the block boundary, selecting one of a plurality of at least three filters, and filtering a plurality of pixels around the block boundary according to the filtering range, the region mode, and the selected filter.

Abstract: A post processing de-blocking filter includes a threshold determination unit for adaptively determining a plurality of threshold values according to at least differences in quantization parameters QPs of a plurality of adjacent blocks in a received video stream and to a user defined offset (UDO) allowing the threshold levels to be adjusted according to the UDO value; an interpolation unit for performing an interpolation operation to estimate pixel values in an interlaced field if the video stream comprises interlaced video; and a de-blocking filtering unit for determining a filtering range specifying a maximum number of pixels to filter around a block boundary between the adjacent blocks, determining a region mode according to local activity around the block boundary, selecting one of a plurality of at least three filters, and filtering a plurality of pixels around the block boundary according to the filtering range, the region mode, and the selected filter.

Abstract: A post processing de-blocking filter includes a threshold determination unit for adaptively determining a plurality of threshold values according to at least differences in quantization parameters QPs of a plurality of adjacent blocks in a received video stream and to a user defined offset (UDO) allowing the threshold levels to be adjusted according to the UDO value; an interpolation unit for performing an interpolation operation to estimate pixel values in an interlaced field if the video stream comprises interlaced video; and a de-blocking filtering unit for determining a filtering range specifying a maximum number of pixels to filter around a block boundary between the adjacent blocks, determining a region mode according to local activity around the block boundary, selecting one of a plurality of at least three filters, and filtering a plurality of pixels around the block boundary according to the filtering range, the region mode, and the selected filter.

Abstract: An electronic system for expandably connecting backplanes of hard disks to a motherboard in a RAID includes a plurality of backplanes, and a motherboard having a connector thereon connecting to a first one of the backplanes. Each backplane includes: a first connector mounted on a front edge thereof, the first connector having N ports; and a second connector mounted at a rear edge thereof, the second connector having N ports. Each port of the first connector is electrically connected to each port of the second connector in a predetermined staggered sequence. The backplanes are connected consecutively, such that a previous backplane communicates via the N ports of the second connector thereof with the N ports of the first connector of a next backplane. A same port on the input or the output connector of each of the backplanes is fixed as a data input of each of the backplanes.

Abstract: A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a first semiconductor feature having an anisotropically etched opening including sidewalls. The first semiconductor feature further provide an overlying photoresist layer photolithographically patterned for anisotropically etching a second semiconductor feature opening overlying and encompassing the first semiconductor feature; blanket depositing a polymeric passivation layer over the overlying photoresist layer including covering at least a portion of the sidewalls including polymeric containing residues; and, removing the polymeric passivation layer including a substantial portion of the polymeric containing residues from at least a portion of the sidewalls prior to anisotropically etching the second semiconductor feature.

Abstract: A system is disclosed for an integrated manufacturing execution system, MES, that unifies the production data for a manufactured lot that moves from a current production line to different production lines, and a process is disclosed for reserving tools by a unified MES that checks for manufacturing capacity utilization of the tools.

Abstract: A method for selectively etching a semiconductor feature opening to controllably achieve a critical dimension accuracy including providing a semiconductor wafer including a first opening formed extending through a thickness of at least one dielectric insulating layer and having an uppermost inorganic BARC layer; depositing a photoresist layer over the uppermost BARC layer and patterning the photoresist layer to form an etching pattern for etching a second opening overlying and encompassing the first opening; carrying out a first plasma assisted etching process to etch through a thickness of the BARC layer including a predetermined amount of CO in a plasma etching chemistry to increase an etching resistance of the photoresist layer; and, carrying out a second plasma assisted etching process to etch through a thickness portion of the at least one dielectric insulating layer to form the second opening.

Abstract: A low gloss thermoplastic composition suitable for making article having low gloss and a process for its preparation are disclosed. The composition contains (I) a resinous component that includes (a) a (co)polyalkyl (meth)acrylate rubber characterized that it contains no grafted phase, (b) a poly(vinyl aromatic-co-nitrile)-grafted (co)polyalkyl (meth)acrylate rubber, and (c) a poly(vinylaromatic-co-nitrile), and (II) a gloss-reducing agent that is the reaction product of (d) a compound having two or more maleic anhydride groups per molecule, and (e) a compound having two or more terminal primary amine groups per molecule, with the proviso that the total of the maleic anhydride groups per molecule and the terminal primary amine functional groups per molecule is greater than 4.

Abstract: A method for plasma etching a semiconductor feature to improve an etching profile including providing a semiconductor wafer including a photoresist layer having a photolithographically patterned portion for etching a feature through a thickness portion of at least one underlying dielectric layer; and, plasma treating the photoresist layer with a carbon monoxide (CO) containing plasma to induce a polymeric cross-linking reaction at the photoresist layer surface to decrease a photoresist layer etching rate in a subsequent etching process; and, etching said feature through the thickness portion to maintain a width dimension of said feature including the photolithographically patterned portion within a pre-determined dimensional variation.

Abstract: A method for protecting a silicon semiconductor wafer backside surface for removing polymer containing residues from a wafer process surface including providing a silicon semiconductor wafer having a process surface and a backside surface said process surface including metal containing features said process surface at least partially covered with polymer containing residues and said backside surface including exposed silicon containing areas; forming an etching resistant oxide layer over the exposed silicon containing areas; and, subjecting the silicon semiconductor wafer to a series of cleaning steps including a wet etchant corrosive to the exposed silicon containing areas.

Abstract: A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a first semiconductor feature having an anisotropically etched opening including sidewalls. The first semiconductor feature further provide an overlying photoresist layer photolithographically patterned for anisotropically etching a second semiconductor feature opening overlying and encompassing the first semiconductor feature; blanket depositing a polymeric passivation layer over the overlying photoresist layer including covering at least a portion of the sidewalls including polymeric containing residues; and, removing the polymeric passivation layer including a substantial portion of the polymeric containing residues from at least a portion of the sidewalls prior to anisotropically etching the second semiconductor feature.

Abstract: A low gloss thermoplastic composition suitable for making article having low gloss and a process for its preparation are disclosed. The composition contains (I) a resinous component that includes (a) a (co)polyalkyl (meth)acrylate rubber characterized that it contains no grafted phase, (b) a poly(vinyl aromatic-co-nitrile)-grafted (co)polyalkyl (meth)acrylate rubber, and (c) a poly(vinylaromatic-co-nitrile), and (II)a gloss-reducing agent that is the reaction product of (d) a compound having two or more maleic anhydride groups per molecule, and (e) a compound having two or more terminal primary amine groups per molecule, with the proviso that the total of the maleic anhydride groups per molecule and the terminal primary amine functional groups per molecule is greater than 4.

Abstract: A method for protecting a silicon semiconductor wafer backside surface for removing polymer containing residues from a wafer process surface including providing a silicon semiconductor wafer having a process surface and a backside surface said process surface including metal containing features said process surface at least partially covered with polymer containing residues and said backside surface including exposed silicon containing areas; forming an etching resistant oxide layer over the exposed silicon containing areas; and, subjecting the silicon semiconductor wafer to a series of cleaning steps including a wet etchant corrosive to the exposed silicon containing areas.