Patents by Inventor Ying Chang
Ying Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145632Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.Type: ApplicationFiled: October 23, 2023Publication date: May 2, 2024Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG
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Publication number: 20240145630Abstract: A light-emitting device includes a substrate and an epitaxial structure. The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer which are disposed on the upper surface of the substrate in such order. The substrate has a substrate edge region surrounding and exposed from the epitaxial structure. The substrate edge region includes a first substrate edge region and a second substrate edge region which is more proximate to the epitaxial structure than the first substrate edge region. The first substrate edge region has a first uneven toothed surface or an even flat surface. The second substrate edge regions are formed with second uneven toothed surfaces which have a height greater than a height of the first even toothed surface, or the even flat surface.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Inventors: Minyou HE, Xiaoliang LIU, Qing WANG, Ling-Yuan HONG, Chung-Ying CHANG
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Publication number: 20240145627Abstract: An epitaxial structure of a semiconductor light-emitting element includes an n-type layer, a V-pit control layer, a light-emitting layer, and a p-type layer stacked from bottom to top. The light-emitting layer includes a plurality of well layers and a plurality of barrier layers stacked alternately. The V-pit control layer includes a first superlattice layer, and a distance between a bottom surface of the V-pit control layer and a bottom surface of the first superlattice layer is less than or equal to 0.15 ?m. The bottom surface of the first superlattice layer and a bottom surface of the light-emitting layer have a distance therebetween ranging from 0.05 ?m to 0.3 ?m, and each of the first superlattice layer and the light-emitting layer is an Indium (In)-containing layer. A semiconductor light-emitting element and a light-emitting device are also provided.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Inventors: Meng-Hsin YEH, Zhousheng JIANG, Bing-Yang CHEN, Dongpo CHEN, Chung-Ying CHANG
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Publication number: 20240142748Abstract: An optical system is provided. The optical system is used for disposing on an electronic device. The optical system includes a movable portion, a fixed portion, a first driving assembly, and a support module. The movable portion is used for connecting to an optical module. The fixed portion is affixed on the electronic device, and the movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the movable portion to move relative to the fixed portion. The movable portion is movably connected to the fixed portion through the support module.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: Ying-Jen WANG, Ya-Hsiu WU, Chen-Chi KUO, Chao-Chang HU, Yi-Ho CHEN, Che-Wei CHANG, Ko-Lun CHAO, Sin-Jhong SONG
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Publication number: 20240141653Abstract: A panel which may be used as a part of a surface covering system, such as that for a wall or a ceiling, and which is useful to provide easy installation, durability, beneficial fire preventive performance, resistance to mold growth, and resistance to moisture. The panels may have a first major surface, a second major surface opposite the first major surface, and a side surface extending between the first and second major surfaces. The panel may be formed from polyvinyl chloride present in an amount from about 45 to about 70 wt. %; carbonate present in an amount from about 10 to about 31 wt. %; stearate present in an amount from about 1 to about 6 wt. %; and aluminum hydroxide present in an amount from about 10 to about 30 wt. %.Type: ApplicationFiled: October 11, 2022Publication date: May 2, 2024Inventors: Ying CHANG, Alan BRIAN, Robert A. DUSCHL, Edward ROBERTS, Carlos X. MEDINA, Ronnie MASSEY, Amber C. ARNOLD, Philip WEBER
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Publication number: 20240142664Abstract: Two types of blue light blocking contact lenses are provided and are formed by curing different compositions. The first composition includes a blue light blocking component formed by mixing or reacting a first hydrophilic monomer and a yellow dye, a first colored dye component formed by mixing or reacting a second hydrophilic monomer and a first colored dye, at least one third hydrophilic monomer, a crosslinker, and an initiator. The first colored dye includes a green dye, a cyan dye, a blue dye, an orange dye, a red dye, a black dye, or combinations thereof. The second composition includes a blue light blocking component, at least one hydrophilic monomer, a crosslinker, and an initiator. The blue light blocking component is formed by mixing or reacting glycerol monomethacrylate and a yellow dye. Further, methods for preparing the above contact lenses are provided.Type: ApplicationFiled: February 12, 2023Publication date: May 2, 2024Inventors: Han-Yi CHANG, Chun-Han CHEN, Tsung-Kao HSU, Wei-che WANG, Yu-Hung LIN, Wan-Ying GAO, Li-Hao LIU
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Patent number: 11973124Abstract: In method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.Type: GrantFiled: January 18, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Wei Chang, Shahaji B. More, Yi-Ying Liu, Yueh-Ching Pai
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Publication number: 20240137875Abstract: A method for adjusting time-averaged (TA) parameters of a transmitting (TX) power of a radio module includes: obtaining at least one message of the at least one other radio module or at least one message of the radio module; determining a scenario of the TX power of the radio module according to the at least one message of the at least one other radio module or the at least one message of the radio module; determining whether the scenario is different from a predetermined scenario of the TX power of the radio module; and in response to the scenario being different from the predetermined scenario, adjusting the TA parameters according to the scenario.Type: ApplicationFiled: October 1, 2023Publication date: April 25, 2024Applicant: MEDIATEK INC.Inventors: Yi-Ying Huang, Yi-Hsuan Lin, Han-Chun Chang
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Patent number: 11968512Abstract: In an example, a speaker device may include a first transducer and a second transducer. The first transducer may include a first diaphragm, a first magnetic circuit, and a first voice coil disposed in a magnetic gap of the first magnetic circuit to cause vibration of the first diaphragm. The second transducer may include a second diaphragm, a second magnet circuit, and a second voice coil disposed in a magnetic gap of the second magnetic circuit to cause vibration of the second diaphragm. Further, the speaker device may include a magnetic plate having a first surface coupled to the first transducer and a second surface coupled to the second transducer. The first surface is opposite to the second surface.Type: GrantFiled: June 22, 2022Date of Patent: April 23, 2024Assignee: Hewlett-Packard Development Company, L.P.Inventors: Yen-Hsin Ho, Yi-Ying Lai, Chen-Hui Hu, Chen-Yu Chang
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Patent number: 11964881Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
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Publication number: 20240128375Abstract: A method includes forming first and second semiconductor fins and a gate structure over a substrate; forming a first and second source/drain epitaxy structures over the first and second semiconductor fins; forming an interlayer dielectric (ILD) layer over the first and second source/drain epitaxy structures; etching the gate structure and the ILD layer to form a trench; performing a first surface treatment to modify surfaces of a top portion and a bottom portion of the trench to NH-terminated; performing a second surface treatment to modify the surfaces of the top portion of the trench to N-terminated, while leaving the surfaces of the bottom portion of the trench being NH-terminated; and depositing a first dielectric layer in the trench, wherein the first dielectric layer has a higher deposition rate on the surfaces of the bottom portion of the trench than on the surfaces of the bottom portion of the trench.Type: ApplicationFiled: March 16, 2023Publication date: April 18, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Yi CHANG, Yu Ying CHEN, Zhen-Cheng WU, Chi On CHUI
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Patent number: 11962247Abstract: A resonant half-bridge flyback power converter includes: a first transistor and a second transistor which form a half-bridge circuit; a transformer and a resonant capacitor connected in series and coupled to the half-bridge circuit; and a switching control circuit configured to generate a first driving signal and a second driving signal to control the first transistor and the second transistor respectively for switching the transformer to generate an output voltage. The first driving signal is configured to magnetize the transformer. The second driving signal includes at most one pulse between two consecutive pulses of the first driving signal. The switching control circuit generates a skipping cycle period when an output power is lower than a predetermined threshold. A resonant pulse of the second driving signal is skipped during the skipping cycle period. The skipping cycle period is increased in response to the decrease of the output power.Type: GrantFiled: February 16, 2022Date of Patent: April 16, 2024Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Ta-Yung Yang, Ying-Chieh Su, Yu-Chang Chen
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Patent number: 11959834Abstract: A manufacturing method of a sample collection component, by which a removable light shielding component is disposed on a main body of the sample collection component to shield at least a portion of the light that passes through a storing space of the sample collection component.Type: GrantFiled: June 16, 2023Date of Patent: April 16, 2024Assignee: Materials Analysis Technology Inc.Inventors: Pin Chang, Ying-Chan Hung, Hung-Jen Chen
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Patent number: 11955191Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.Type: GrantFiled: June 2, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang
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Patent number: 11955329Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.Type: GrantFiled: April 28, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
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Patent number: 11955553Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: February 24, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Publication number: 20240113258Abstract: A light-emitting diode (LED) includes a semiconductor structure, a transparent conducting layer, a first electrode, and a second electrode. The semiconductor structure has a lower surface and an upper surface, and includes a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked in a laminating direction from the lower surface to the upper surface. The transparent conducting layer is located on the second semiconductor layer. The first electrode is located on the first semiconductor layer. The second electrode is located on the transparent conducting layer. When viewing the semiconductor structure and the transparent conducting layer from above the LED. The semiconductor structure has a shortest side with a length of X ?m.Type: ApplicationFiled: September 27, 2023Publication date: April 4, 2024Applicant: Quanzhou San'an Semiconductor Technology Co., Ltd.Inventors: Liming ZHANG, Renlong YANG, Heying TANG, Quanyang MA, Xingrong CHEN, Chung-Ying CHANG
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Publication number: 20240113259Abstract: A light-emitting device includes a semiconductor epitaxial structure including a first semiconductor layer, an active layer, and a second semiconductor layer, and having holes; a first insulation layer disposed on the semiconductor epitaxial structure and having first and second grooves; a first pad electrically connected to the first semiconductor layer through the first grooves; and a second pad electrically connected to the second semiconductor layer through the second grooves. A projection of the first pad does not overlap projections of the holes. A projection of the second pad does not overlap the projections of the holes. The first pad includes a first pad connection portion and first pad extension portions; the second pad includes a second pad connection portion and second pad extension portions. Projections of the second grooves fall between projections of the first and second pad extension portions. Two other aspects of the light-emitting device are also provided.Type: ApplicationFiled: September 28, 2023Publication date: April 4, 2024Inventors: Xiushan ZHU, Qi JING, Yan LI, Xiaoliang LIU, Zhilong LU, Chunhsien LEE, Chi-Ming TSAI, Juchin TU, Chung-Ying CHANG
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Publication number: 20240113187Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Jhu-Min Song, Ying-Chou Chen, Yi-Kai Ciou, Chien-Chih Chou, Fei-Yun Chen, Yu-Chang Jong, Chi-Te Lin
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Publication number: 20240105879Abstract: A light-emitting diode and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, an LED wafer is provided. The LED wafer includes a substrate and a light-emitting semiconductor stacking structure positioned on the surface of the substrate. The light-emitting semiconductor stacking structure includes a first type semiconductor layer, an active layer, and a second type semiconductor layer from a side of the substrate. Second, dicing lanes are defined on the upper surface of the LED wafer. Third, dicing is performed along the dicing lanes of the substrate using a laser. The laser is focused on the lower surface of the substrate to form a surface hole and focused inside the substrate to form an internal hole. The diameter of the surface hole is greater than the diameter of the internal hole. Fourth, the LED wafer is separated into LED chips along the dicing lanes.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: Quanzhou sanan semiconductor technology Co., Ltd.Inventors: TSUNG-MING LIN, CHUNG-YING CHANG, YI-JUI HUANG, YU-TSAI TENG